Differential D17869

cxgbe: Fix false sharing between t4_nm_intr and cxgbe_netmap_rxsync
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Authored by bwicht_verisign.com on Nov 6 2018, 1:23 PM.

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Summary

Split sge_nm_rxq fields into three cachelines.

Submitted by: Marc De La Gueronniere <mdelagueronniere@verisign.com>
MFC after: 1 week
Sponsored by: Verisign, Inc.

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Build Status

Buildable 20659
Build 20074: arc lint + arc unit

Event Timeline

bwicht_verisign.com created this revision.Nov 6 2018, 1:23 PM

Herald added a subscriber: ae. · View Herald TranscriptNov 6 2018, 1:23 PM

Harbormaster completed remote builds in B20659: Diff 50072.Nov 6 2018, 1:23 PM

How about using __aligned(CACHE_LINE_SIZE) like the rest of the driver and let the compiler figure out the padding?

This revision now requires changes to proceed.Nov 6 2018, 5:34 PM

jch added a subscriber: jch.Nov 6 2018, 9:29 PM

Use __aligned(CACHE_LINE_SIZE) instead of manual padding

Harbormaster completed remote builds in B20677: Diff 50108.Nov 7 2018, 9:28 AM

In D17869#381863, @np wrote:

How about using __aligned(CACHE_LINE_SIZE) like the rest of the driver and let the compiler figure out the padding?

Excellent idea!

I just did the change.

Thanks, Navdeep.

np mentioned this in rS359159: cxgbe(4): Split sge_nm_rxq into three cachelines..Mar 20 2020, 5:12 AM

Can you please try r359159?

np mentioned this in rS359351: MFC r359159:.Mar 27 2020, 3:58 AM

Revision Contents
Changeset List

Path

Size

sys/

dev/

cxgbe/

adapter.h

17 lines

Diff 50072

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cxgbe: Fix false sharing between t4_nm_intr and cxgbe_netmap_rxsyncNeeds ReviewPublicActions