diff --git a/sys/arm64/arm64/gic_v3.c b/sys/arm64/arm64/gic_v3.c
--- a/sys/arm64/arm64/gic_v3.c
+++ b/sys/arm64/arm64/gic_v3.c
@@ -382,6 +382,13 @@
 
 	mtx_init(&sc->gic_mbi_mtx, "GICv3 mbi lock", NULL, MTX_DEF);
 	if (sc->gic_mbi_start > 0) {
+		if (!sc->gic_mbi_end) {
+			/*
+			 * This is to address SPI based msi ranges, where
+			 * SPI range is not specified in ACPI
+			 */
+			sc->gic_mbi_end = sc->gic_nirqs - 1;
+		}
 		gic_v3_reserve_msi_range(dev, sc->gic_mbi_start,
 		    sc->gic_mbi_end - sc->gic_mbi_start);
 
diff --git a/sys/arm64/arm64/gic_v3_acpi.c b/sys/arm64/arm64/gic_v3_acpi.c
--- a/sys/arm64/arm64/gic_v3_acpi.c
+++ b/sys/arm64/arm64/gic_v3_acpi.c
@@ -50,6 +50,8 @@
 
 #define	GICV3_PRIV_VGIC		0x80000000
 #define	GICV3_PRIV_FLAGS	0x80000000
+#define HV_MSI_SPI_START 	64
+#define HV_MSI_SPI_LAST 	0
 
 struct gic_v3_acpi_devinfo {
 	struct gic_v3_devinfo	di_gic_dinfo;
@@ -319,7 +321,10 @@
 	err = gic_v3_acpi_count_regions(dev);
 	if (err != 0)
 		goto count_error;
-
+	if (vm_guest == VM_GUEST_HV) {
+		sc->gic_mbi_start = HV_MSI_SPI_START;
+		sc->gic_mbi_end = HV_MSI_SPI_LAST;
+	}
 	err = gic_v3_attach(dev);
 	if (err != 0)
 		goto error;
@@ -330,6 +335,17 @@
 		err = ENXIO;
 		goto error;
 	}
+	/*
+	 * Registering for MSI with SPI rnage, as this is
+	 * required for Hyper-V GIC to work in ARM64.
+	 */
+	if (vm_guest == VM_GUEST_HV) {
+		err = intr_msi_register(dev, ACPI_MSI_XREF);
+		if (err) {
+			device_printf(dev, "could not register MSI\n");
+			goto error;
+		}
+	}
 
 	if (intr_pic_claim_root(dev, ACPI_INTR_XREF, arm_gic_v3_intr, sc,
 	    GIC_LAST_SGI - GIC_FIRST_SGI + 1) != 0) {