diff --git a/share/man/man4/Makefile b/share/man/man4/Makefile --- a/share/man/man4/Makefile +++ b/share/man/man4/Makefile @@ -501,6 +501,7 @@ random.4 \ rctl.4 \ re.4 \ + rge.4 \ rgephy.4 \ rights.4 \ rl.4 \ diff --git a/share/man/man4/rge.4 b/share/man/man4/rge.4 new file mode 100644 --- /dev/null +++ b/share/man/man4/rge.4 @@ -0,0 +1,165 @@ +.\" +.\" Copyright (c) 2025 Adrian Chadd +.\" +.\" SPDX-License-Identifier: BSD-2-Clause +.\" +.Dd December 12, 2025 +.Dt RGE 4 +.Os +.Sh NAME +.Nm rge +.Nd RealTek RTL8125/RTL8126/RTL8127/Killer E3000 PCIe Ethernet adapter driver +.Sh SYNOPSIS +To compile this driver into the kernel, +place the following lines in your +kernel configuration file: +.Bd -ragged -offset indent +.Cd "device rge" +.Ed +.Pp +Alternatively, to load the driver as a +module at boot time, place the following line in +.Xr loader.conf 5 : +.Bd -literal -offset indent +if_rge_load="YES" +.Ed +.Sh DESCRIPTION +The +.Nm +driver provides support for various NICs based on the RealTek RTL8125, +RTL8126 and RTL8127 PCIe Ethernet controllers. +.Pp +All of the NICs supported by this driver support 10, 100 and 1000Mbit +over CAT5 cable. +NICs based on the RTL8125 additionally support 2.5Gbit over CAT6 cable. +NICs based on the RTL8126 additionally support 2.5Gbit and 5Gbit over CAT6 +cable. +NICs based on the RTL8127 additionally support 2.5Gbit, 5Gbit and 10Gbit +over CAT6 cable. +.Pp +All NICs supported by the +.Nm +driver have TCP/IP checksum offload and hardware VLAN tagging/insertion +features, and use a descriptor-based DMA mechanism. +They are also +capable of TCP large send (TCP segmentation offload). +.Pp +The RTL8125, RTL8126 and RTL8127 devices are single-chip solutions combining +both a MAC and PHY. +Standalone cards are available in 1x PCIe models. +.Pp +The RTL8125, RTL8126 and RTL8127 also support jumbo frames, which can be +configured via the interface MTU setting. +The MTU is limited to 9126. +Selecting an MTU larger than 1500 bytes with the +.Xr ifconfig 8 +utility configures the adapter to receive and transmit jumbo frames. +.Pp +The +.Nm +driver supports the following media types: +.Bl -tag -width "10baseT/UTP" +.It Cm autoselect +Enable autoselection of the media type and options. +The user can manually override +the autoselected mode by adding media options to +.Xr rc.conf 5 . +.It Cm 10baseT/UTP +Set 10Mbps operation. +The +.Xr ifconfig 8 +.Cm mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 100baseTX +Set 100Mbps (Fast Ethernet) operation. +The +.Xr ifconfig 8 +.Cm mediaopt +option can also be used to select either +.Cm full-duplex +or +.Cm half-duplex +modes. +.It Cm 1000baseTX +Set 1000baseTX operation over twisted pair. +The RealTek gigE chips support 1000Mbps in +.Cm full-duplex +mode only. +.It Cm 2500baseTX +Set 2500baseTX operation over twisted pair. +The RealTek devices support 2.5Gbit in +.Cm full-duplex +mode only. +.It Cm 5000baseTX +Set 5000baseTX operation over twisted pair. +The RealTek devices support 5Gbit in +.Cm full-duplex +mode only. +.It Cm 10000baseTX +Set 10000baseTX operation over twisted pair. +The RealTek devices support 10Gbit in +.Cm full-duplex +mode only. +.El +.Pp +The +.Nm +driver supports the following media options: +.Bl -tag -width "full-duplex" +.It Cm full-duplex +Force full duplex operation. +.It Cm half-duplex +Force half duplex operation. +.El +.Pp +For more information on configuring this device, see +.Xr ifconfig 8 . +.Sh HARDWARE +The +.Nm +driver supports RealTek RTL8125, RTL8126, RTL8125 and Killer E3000 based +PCIe 1GB to 1GB Ethernet devices. +.Sh SYSCTL VARIABLES +The following variables are available as both +.Xr sysctl 8 +variables and +.Xr loader 8 +tunables: +.Bl -tag -width "xxxxxx" +.It Va dev.rge.%d.debug +Configure runtime debug output. This is a 32 bit bitmask. +.El +.Sh DIAGNOSTICS +.Bl -diag +.It "rge%d: watchdog timeout" +The device has stopped responding to the network, or there is a problem with +the network connection (cable). +.El +.Sh SEE ALSO +.Xr altq 4 , +.Xr arp 4 , +.Xr miibus 4 , +.Xr netintro 4 , +.Xr ng_ether 4 , +.Xr polling 4 , +.Xr vlan 4 , +.Xr ifconfig 8 +.Rs +.%U https://www.realtek.com/ +.Re +.Sh HISTORY +The +.Nm +device driver first appeared in +.Fx 16.0 . +.Sh AUTHORS +The +.Nm +driver was written by +.An Kevin Lo Aq Mt kevlo@openbsd.org +and ported to FreeBSD by +.An Adrian Chadd Aq Mt adrian@freebsd.org . diff --git a/sys/conf/files b/sys/conf/files --- a/sys/conf/files +++ b/sys/conf/files @@ -2866,6 +2866,10 @@ dev/regulator/regulator.c optional regulator dev/regulator/regulator_bus.c optional regulator fdt dev/regulator/regulator_fixed.c optional regulator +dev/rge/if_rge.c optional rge +dev/rge/if_rge_hw.c optional rge +dev/rge/if_rge_stats.c optional rge +dev/rge/if_rge_sysctl.c optional rge dev/rl/if_rl.c optional rl pci dev/rndtest/rndtest.c optional rndtest # diff --git a/sys/dev/rge/if_rge.c b/sys/dev/rge/if_rge.c new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge.c @@ -0,0 +1,2683 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2023-2025 Kevin Lo + * Copyright (c) 2025 Adrian Chadd + * + * Hardware programming portions from Realtek Semiconductor. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rge.c,v 1.38 2025/09/19 00:41:14 kevlo Exp $ */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include "if_rge_vendor.h" +#include "if_rgereg.h" +#include "if_rgevar.h" +#include "if_rge_hw.h" +#include "if_rge_microcode.h" +#include "if_rge_debug.h" +#include "if_rge_sysctl.h" +#include "if_rge_stats.h" + +#define RGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) + +static int rge_attach(device_t); +static int rge_detach(device_t); + +#if 0 +int rge_activate(struct device *, int); +#endif +static void rge_intr_msi(void *); +static int rge_ioctl(struct ifnet *, u_long, caddr_t); +static int rge_transmit_if(if_t, struct mbuf *); +static void rge_qflush_if(if_t); +static void rge_init_if(void *); +static void rge_init_locked(struct rge_softc *); +static void rge_stop_locked(struct rge_softc *); +static int rge_ifmedia_upd(if_t); +static void rge_ifmedia_sts(if_t, struct ifmediareq *); +static int rge_allocmem(struct rge_softc *); +static int rge_alloc_stats_mem(struct rge_softc *); +static int rge_freemem(struct rge_softc *); +static int rge_free_stats_mem(struct rge_softc *); +static int rge_newbuf(struct rge_queues *); +static void rge_rx_list_init(struct rge_queues *); +static void rge_tx_list_init(struct rge_queues *); +static void rge_fill_rx_ring(struct rge_queues *); +static int rge_rxeof(struct rge_queues *, struct mbufq *); +static int rge_txeof(struct rge_queues *); +static void rge_iff_locked(struct rge_softc *); +static void rge_add_media_types(struct rge_softc *); +static void rge_tx_task(void *, int); +static void rge_txq_flush_mbufs(struct rge_softc *sc); +static void rge_tick(void *); +static void rge_link_state(struct rge_softc *); +#if 0 +#ifndef SMALL_KERNEL +int rge_wol(struct ifnet *, int); +void rge_wol_power(struct rge_softc *); +#endif +#endif + +struct rge_matchid { + uint16_t vendor; + uint16_t device; + const char *name; +}; + +const struct rge_matchid rge_devices[] = { + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_E3000, "Killer E3000" }, + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8125, "RTL8125" }, + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8126, "RTL8126", }, + { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RTL8127, "RTL8127" }, + { 0, 0, NULL } +}; + +static int +rge_probe(device_t dev) +{ + uint16_t vendor, device; + const struct rge_matchid *ri; + + vendor = pci_get_vendor(dev); + device = pci_get_device(dev); + + for (ri = rge_devices; ri->name != NULL; ri++) { + if ((vendor == ri->vendor) && (device == ri->device)) { + device_set_desc(dev, ri->name); + return (BUS_PROBE_DEFAULT); + } + } + + return (ENXIO); +} + +static void +rge_attach_if(struct rge_softc *sc, const char *eaddr) +{ + if_initname(sc->sc_ifp, device_get_name(sc->sc_dev), + device_get_unit(sc->sc_dev)); + if_setdev(sc->sc_ifp, sc->sc_dev); + if_setinitfn(sc->sc_ifp, rge_init_if); + if_setsoftc(sc->sc_ifp, sc); + if_setflags(sc->sc_ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); + if_setioctlfn(sc->sc_ifp, rge_ioctl); + if_settransmitfn(sc->sc_ifp, rge_transmit_if); + if_setqflushfn(sc->sc_ifp, rge_qflush_if); + + /* Set offload as appropriate */ + if_sethwassist(sc->sc_ifp, CSUM_IP | CSUM_TCP | CSUM_UDP); + if_setcapabilities(sc->sc_ifp, IFCAP_HWCSUM); + if_setcapenable(sc->sc_ifp, if_getcapabilities(sc->sc_ifp)); + + /* TODO: set WOL */ + + /* Attach interface */ + ether_ifattach(sc->sc_ifp, eaddr); + sc->sc_ether_attached = true; + + /* post ether_ifattach() bits */ + + /* VLAN capabilities */ + if_setcapabilitiesbit(sc->sc_ifp, IFCAP_VLAN_MTU | + IFCAP_VLAN_HWTAGGING, 0); + if_setcapabilitiesbit(sc->sc_ifp, IFCAP_VLAN_HWCSUM, 0); + if_setcapenable(sc->sc_ifp, if_getcapabilities(sc->sc_ifp)); + + if_setifheaderlen(sc->sc_ifp, sizeof(struct ether_vlan_header)); + + /* TODO: is this needed for iftransmit? */ + if_setsendqlen(sc->sc_ifp, RGE_TX_LIST_CNT - 1); + if_setsendqready(sc->sc_ifp); +} + +static int +rge_attach(device_t dev) +{ + uint8_t eaddr[ETHER_ADDR_LEN]; + struct rge_softc *sc; + struct rge_queues *q; + uint32_t hwrev, reg; + int i, rid; + int error; + int msic; + + sc = device_get_softc(dev); + sc->sc_dev = dev; + sc->sc_ifp = if_gethandle(IFT_ETHER); + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF); + + /* Enable bus mastering */ + pci_enable_busmaster(dev); + + /* + * Map control/status registers. + */ + + /* + * The openbsd driver (and my E3000 NIC) handle registering three + * kinds of BARs - a 64 bit MMIO BAR, a 32 bit MMIO BAR, and then + * a legacy IO port BAR. + * + * To simplify bring-up, I'm going to request resources for the first + * MMIO BAR (BAR2) which should be a 32 bit BAR. + */ + rid = PCIR_BAR(2); + sc->sc_bres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, + RF_ACTIVE); + if (sc->sc_bres == NULL) { + RGE_PRINT_ERROR(sc, + "Unable to allocate bus resource: memory\n"); + goto fail; + } + sc->rge_bhandle = rman_get_bushandle(sc->sc_bres); + sc->rge_btag = rman_get_bustag(sc->sc_bres); + sc->rge_bsize = rman_get_size(sc->sc_bres); + + q = malloc(sizeof(struct rge_queues), M_DEVBUF, M_NOWAIT | M_ZERO); + if (q == NULL) { + RGE_PRINT_ERROR(sc, "Unable to malloc rge_queues memory\n"); + goto fail; + } + q->q_sc = sc; + q->q_index = 0; + + sc->sc_queues = q; + sc->sc_nqueues = 1; + + /* Check if PCIe */ + if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { + sc->rge_flags |= RGE_FLAG_PCIE; + sc->sc_expcap = reg; + } + + /* Allocate MSI */ + msic = pci_msi_count(dev); + if (msic == 0) { + RGE_PRINT_ERROR(sc, "%s: only MSI interrupts supported\n", + __func__); + goto fail; + } + + msic = RGE_MSI_MESSAGES; + if (pci_alloc_msi(dev, &msic) != 0) { + RGE_PRINT_ERROR(sc, "%s: failed to allocate MSI\n", + __func__); + goto fail; + } + + sc->rge_flags |= RGE_FLAG_MSI; + + /* We need at least one MSI */ + if (msic < RGE_MSI_MESSAGES) { + RGE_PRINT_ERROR(sc, "%s: didn't allocate enough MSI\n", + __func__); + goto fail; + } + + /* + * Allocate interrupt entries. + */ + for (i = 0, rid = 1; i < RGE_MSI_MESSAGES; i++, rid++) { + sc->sc_irq[i] = bus_alloc_resource_any(dev, SYS_RES_IRQ, + &rid, RF_ACTIVE); + if (sc->sc_irq[i] == NULL) { + RGE_PRINT_ERROR(sc, "%s: couldn't allocate MSI %d", + __func__, rid); + goto fail; + } + } + + /* Hook interrupts */ + for (i = 0; i < RGE_MSI_MESSAGES; i++) { + error = bus_setup_intr(dev, sc->sc_irq[i], + INTR_TYPE_NET | INTR_MPSAFE, NULL, rge_intr_msi, + sc, &sc->sc_ih[i]); + if (error != 0) { + RGE_PRINT_ERROR(sc, + "%s: couldn't setup intr %d (error %d)", __func__, + i, error); + goto fail; + } + } + + /* Allocate top level bus DMA tag */ + error = bus_dma_tag_create(bus_get_dma_tag(dev), + 1, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + BUS_SPACE_MAXADDR, /* maxsize */ + BUS_SPACE_UNRESTRICTED, /* nsegments */ + BUS_SPACE_MAXADDR, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device DMA tag (error %d)\n", error); + goto fail; + } + + /* Allocate TX/RX descriptor and buffer tags */ + error = bus_dma_tag_create(sc->sc_dmat, + RGE_ALIGN, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + RGE_TX_LIST_SZ, /* maxsize */ + 1, /* nsegments */ + RGE_TX_LIST_SZ, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat_tx_desc); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device TX descriptor " + "DMA tag (error %d)\n", error); + goto fail; + } + + error = bus_dma_tag_create(sc->sc_dmat, + 1, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + RGE_JUMBO_FRAMELEN, /* maxsize */ + RGE_TX_NSEGS, /* nsegments */ + RGE_JUMBO_FRAMELEN, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat_tx_buf); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device TX buffer DMA tag (error %d)\n", + error); + goto fail; + } + + error = bus_dma_tag_create(sc->sc_dmat, + RGE_ALIGN, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + RGE_RX_LIST_SZ, /* maxsize */ + 1, /* nsegments */ + RGE_RX_LIST_SZ, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat_rx_desc); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device RX descriptor " + "DMA tag (error %d)\n", error); + goto fail; + } + + error = bus_dma_tag_create(sc->sc_dmat, + 1, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + MCLBYTES, /* maxsize */ + 1, /* nsegments */ + MCLBYTES, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat_rx_buf); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device RX buffer DMA tag (error %d)\n", + error); + goto fail; + } + + error = bus_dma_tag_create(sc->sc_dmat, + RGE_STATS_ALIGNMENT, /* alignment */ + 0, /* boundary */ + BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, + NULL, NULL, /* filter (unused) */ + RGE_STATS_BUF_SIZE, /* maxsize */ + 1, /* nsegments */ + RGE_STATS_BUF_SIZE, /* maxsegsize */ + 0, /* flags */ + NULL, NULL, /* lockfunc, lockarg */ + &sc->sc_dmat_stats_buf); + if (error) { + RGE_PRINT_ERROR(sc, + "couldn't allocate device RX buffer DMA tag (error %d)\n", + error); + goto fail; + } + + + /* Attach sysctl nodes */ + rge_sysctl_attach(sc); + + /* Determine hardware revision */ + hwrev = RGE_READ_4(sc, RGE_TXCFG) & RGE_TXCFG_HWREV; + switch (hwrev) { + case 0x60900000: + sc->rge_type = MAC_R25; +// device_printf(dev, "RTL8125\n"); + break; + case 0x64100000: + sc->rge_type = MAC_R25B; +// device_printf(dev, "RTL8125B\n"); + break; + case 0x64900000: + sc->rge_type = MAC_R26; +// device_printf(dev, "RTL8126\n"); + break; + case 0x68800000: + sc->rge_type = MAC_R25D; +// device_printf(dev, "RTL8125D\n"); + break; + case 0x6c900000: + sc->rge_type = MAC_R27; +// device_printf(dev, "RTL8127\n"); + break; + default: + RGE_PRINT_ERROR(sc, "unknown version 0x%08x\n", hwrev); + goto fail; + } + + rge_config_imtype(sc, RGE_IMTYPE_SIM); + + /* TODO: disable ASPM/ECPM? */ + +#if 0 + /* + * PCI Express check. + */ + if (pci_get_capability(pa->pa_pc, pa->pa_tag, PCI_CAP_PCIEXPRESS, + &offset, NULL)) { + /* Disable PCIe ASPM and ECPM. */ + reg = pci_conf_read(pa->pa_pc, pa->pa_tag, + offset + PCI_PCIE_LCSR); + reg &= ~(PCI_PCIE_LCSR_ASPM_L0S | PCI_PCIE_LCSR_ASPM_L1 | + PCI_PCIE_LCSR_ECPM); + pci_conf_write(pa->pa_pc, pa->pa_tag, offset + PCI_PCIE_LCSR, + reg); + } +#endif + + RGE_LOCK(sc); + if (rge_chipinit(sc)) { + RGE_UNLOCK(sc); + goto fail; + } + + rge_get_macaddr(sc, eaddr); + RGE_UNLOCK(sc); + + if (rge_allocmem(sc)) + goto fail; + if (rge_alloc_stats_mem(sc)) + goto fail; + + /* Initialize ifmedia structures. */ + ifmedia_init(&sc->sc_media, IFM_IMASK, rge_ifmedia_upd, + rge_ifmedia_sts); + rge_add_media_types(sc); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_AUTO, 0, NULL); + ifmedia_set(&sc->sc_media, IFM_ETHER | IFM_AUTO); + sc->sc_media.ifm_media = sc->sc_media.ifm_cur->ifm_media; + + rge_attach_if(sc, eaddr); + + /* + * TODO: technically should be per txq but we only support + * one TXQ at the moment. + */ + mbufq_init(&sc->sc_txq, RGE_TX_LIST_CNT); + + snprintf(sc->sc_tq_name, sizeof(sc->sc_tq_name), + "%s taskq", device_get_nameunit(sc->sc_dev)); + snprintf(sc->sc_tq_thr_name, sizeof(sc->sc_tq_thr_name), + "%s taskq thread", device_get_nameunit(sc->sc_dev)); + + sc->sc_tq = taskqueue_create(sc->sc_tq_name, M_NOWAIT, + taskqueue_thread_enqueue, &sc->sc_tq); + taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s", + sc->sc_tq_thr_name); + + TASK_INIT(&sc->sc_tx_task, 0, rge_tx_task, sc); + + callout_init_mtx(&sc->sc_timeout, &sc->sc_mtx, 0); + + return (0); +fail: + rge_detach(dev); + return (ENXIO); +} + +/** + * @brief flush the mbufq queue + * + * Again this should likely be per-TXQ. + * + * This should be called with the driver lock held. + */ +static void +rge_txq_flush_mbufs(struct rge_softc *sc) +{ + struct mbuf *m; + int ntx = 0; + + RGE_ASSERT_LOCKED(sc); + + while ((m = mbufq_dequeue(&sc->sc_txq)) != NULL) { + m_freem(m); + ntx++; + } + + RGE_DPRINTF(sc, RGE_DEBUG_XMIT, "%s: %d frames flushed\n", __func__, + ntx); +} + +static int +rge_detach(device_t dev) +{ + struct rge_softc *sc = device_get_softc(dev); + int i, rid; + + /* global flag, detaching */ + RGE_LOCK(sc); + sc->sc_stopped = true; + sc->sc_detaching = true; + RGE_UNLOCK(sc); + + /* stop/drain network interface */ + callout_drain(&sc->sc_timeout); + + /* Make sure TX task isn't running */ + if (sc->sc_tq != NULL) { + while (taskqueue_cancel(sc->sc_tq, &sc->sc_tx_task, NULL) != 0) + taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); + } + + RGE_LOCK(sc); + callout_stop(&sc->sc_timeout); + + /* stop NIC / DMA */ + rge_stop_locked(sc); + + /* TODO: wait for completion */ + + /* Free pending TX mbufs */ + rge_txq_flush_mbufs(sc); + + RGE_UNLOCK(sc); + + /* Free taskqueue */ + if (sc->sc_tq != NULL) { + taskqueue_free(sc->sc_tq); + sc->sc_tq = NULL; + } + + /* Free descriptor memory */ + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: freemem\n", __func__); + rge_freemem(sc); + rge_free_stats_mem(sc); + + if (sc->sc_ifp) { + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: ifdetach/if_free\n", + __func__); + if (sc->sc_ether_attached) + ether_ifdetach(sc->sc_ifp); + if_free(sc->sc_ifp); + } + + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat_tx_desc\n", __func__); + if (sc->sc_dmat_tx_desc) + bus_dma_tag_destroy(sc->sc_dmat_tx_desc); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat_tx_buf\n", __func__); + if (sc->sc_dmat_tx_buf) + bus_dma_tag_destroy(sc->sc_dmat_tx_buf); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat_rx_desc\n", __func__); + if (sc->sc_dmat_rx_desc) + bus_dma_tag_destroy(sc->sc_dmat_rx_desc); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat_rx_buf\n", __func__); + if (sc->sc_dmat_rx_buf) + bus_dma_tag_destroy(sc->sc_dmat_rx_buf); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat_stats_buf\n", __func__); + if (sc->sc_dmat_stats_buf) + bus_dma_tag_destroy(sc->sc_dmat_stats_buf); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: sc_dmat\n", __func__); + if (sc->sc_dmat) + bus_dma_tag_destroy(sc->sc_dmat); + + /* Teardown interrupts */ + for (i = 0; i < RGE_MSI_MESSAGES; i++) { + if (sc->sc_ih[i] != NULL) { + bus_teardown_intr(sc->sc_dev, sc->sc_irq[i], + sc->sc_ih[i]); + sc->sc_ih[i] = NULL; + } + } + + /* Free interrupt resources */ + for (i = 0, rid = 1; i < RGE_MSI_MESSAGES; i++, rid++) { + if (sc->sc_irq[i] != NULL) { + bus_release_resource(sc->sc_dev, SYS_RES_IRQ, + rid, sc->sc_irq[i]); + sc->sc_irq[i] = NULL; + } + } + + /* Free MSI allocation */ + if (sc->rge_flags & RGE_FLAG_MSI) + pci_release_msi(dev); + + if (sc->sc_bres) { + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: release mmio\n", + __func__); + bus_release_resource(dev, SYS_RES_MEMORY, + rman_get_rid(sc->sc_bres), sc->sc_bres); + sc->sc_bres = NULL; + } + + if (sc->sc_queues) { + free(sc->sc_queues, M_DEVBUF); + sc->sc_queues = NULL; + } + + mtx_destroy(&sc->sc_mtx); + + return (0); +} + +#if 0 + +int +rge_activate(struct device *self, int act) +{ +#ifndef SMALL_KERNEL + struct rge_softc *sc = (struct rge_softc *)self; +#endif + + switch (act) { + case DVACT_POWERDOWN: +#ifndef SMALL_KERNEL + rge_wol_power(sc); +#endif + break; + } + return (0); +} +#endif + +static void +rge_intr_msi(void *arg) +{ + struct mbufq rx_mq; + struct epoch_tracker et; + struct mbuf *m; + struct rge_softc *sc = arg; + struct rge_queues *q = sc->sc_queues; + uint32_t status; + int claimed = 0, rv; + + sc->sc_drv_stats.intr_cnt++; + + mbufq_init(&rx_mq, RGE_RX_LIST_CNT); + + if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) == 0) + return; + + RGE_LOCK(sc); + + if (sc->sc_suspended || sc->sc_stopped || sc->sc_detaching) { + RGE_UNLOCK(sc); + return; + } + + /* Disable interrupts. */ + RGE_WRITE_4(sc, RGE_IMR, 0); + + if (!(sc->rge_flags & RGE_FLAG_MSI)) { + if ((RGE_READ_4(sc, RGE_ISR) & sc->rge_intrs) == 0) + goto done; + } + + status = RGE_READ_4(sc, RGE_ISR); + if (status) + RGE_WRITE_4(sc, RGE_ISR, status); + + if (status & RGE_ISR_PCS_TIMEOUT) + claimed = 1; + + rv = 0; + if (status & sc->rge_intrs) { + + (void) q; + rv |= rge_rxeof(q, &rx_mq); + rv |= rge_txeof(q); + + if (status & RGE_ISR_SYSTEM_ERR) { + sc->sc_drv_stats.intr_system_err_cnt++; + rge_init_locked(sc); + } + claimed = 1; + } + + if (sc->rge_timerintr) { + if (!rv) { + /* + * Nothing needs to be processed, fallback + * to use TX/RX interrupts. + */ + rge_setup_intr(sc, RGE_IMTYPE_NONE); + + /* + * Recollect, mainly to avoid the possible + * race introduced by changing interrupt + * masks. + */ + rge_rxeof(q, &rx_mq); + rge_txeof(q); + } else + RGE_WRITE_4(sc, RGE_TIMERCNT, 1); + } else if (rv) { + /* + * Assume that using simulated interrupt moderation + * (hardware timer based) could reduce the interrupt + * rate. + */ + rge_setup_intr(sc, RGE_IMTYPE_SIM); + } + + RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); + +done: + RGE_UNLOCK(sc); + + NET_EPOCH_ENTER(et); + /* Handle any RX frames, outside of the driver lock */ + while ((m = mbufq_dequeue(&rx_mq)) != NULL) { + sc->sc_drv_stats.recv_input_cnt++; + if_input(sc->sc_ifp, m); + } + NET_EPOCH_EXIT(et); + + (void) claimed; +} + +static inline void +rge_tx_list_sync(struct rge_softc *sc, struct rge_queues *q, + unsigned int idx, unsigned int len, int ops) +{ + bus_dmamap_sync(sc->sc_dmat_tx_desc, q->q_tx.rge_tx_list_map, ops); +} + +/** + * @brief Queue the given mbuf at the given TX slot index for transmit. + * + * If the frame couldn't be enqueued then 0 is returned. + * The caller needs to handle that and free/re-queue the mbuf as required. + * + * Note that this doesn't actually kick-start the transmit itself; + * see rge_txstart() for the register to poke to start transmit. + * + * This must be called with the driver lock held. + * + * @param sc driver softc + * @param q TX queue ring + * @param m mbuf to enqueue + * @returns if the mbuf is enqueued, it's consumed here and the number of + * TX descriptors used is returned; if there's no space then 0 is + * returned; if the mbuf couldn't be defragged and the caller + * should free it then -1 is returned. + */ +static int +rge_encap(struct rge_softc *sc, struct rge_queues *q, struct mbuf *m, int idx) +{ + struct rge_tx_desc *d = NULL; + struct rge_txq *txq; + bus_dmamap_t txmap; + uint32_t cmdsts, cflags = 0; + int cur, error, i; + bus_dma_segment_t seg[RGE_TX_NSEGS]; + int nsegs; + + RGE_ASSERT_LOCKED(sc); + + txq = &q->q_tx.rge_txq[idx]; + txmap = txq->txq_dmamap; + + sc->sc_drv_stats.tx_encap_cnt++; + + nsegs = RGE_TX_NSEGS; + error = bus_dmamap_load_mbuf_sg(sc->sc_dmat_tx_buf, txmap, m, + seg, &nsegs, BUS_DMA_NOWAIT); + + switch (error) { + case 0: + break; + case EFBIG: /* mbuf chain is too fragmented */ + sc->sc_drv_stats.tx_encap_refrag_cnt++; + nsegs = RGE_TX_NSEGS; + if (m_defrag(m, M_NOWAIT) == 0 && + bus_dmamap_load_mbuf_sg(sc->sc_dmat_tx_buf, txmap, m, + seg, &nsegs, BUS_DMA_NOWAIT) == 0) + break; + /* FALLTHROUGH */ + default: + sc->sc_drv_stats.tx_encap_err_toofrag++; + return (-1); + } + + bus_dmamap_sync(sc->sc_dmat_tx_buf, txmap, BUS_DMASYNC_PREWRITE); + + /* + * Set RGE_TDEXTSTS_IPCSUM if any checksum offloading is requested. + * Otherwise, RGE_TDEXTSTS_TCPCSUM / RGE_TDEXTSTS_UDPCSUM does not + * take affect. + */ + if ((m->m_pkthdr.csum_flags & RGE_CSUM_FEATURES) != 0) { + cflags |= RGE_TDEXTSTS_IPCSUM; + sc->sc_drv_stats.tx_offload_ip_csum_set++; + if (m->m_pkthdr.csum_flags & CSUM_TCP) { + sc->sc_drv_stats.tx_offload_tcp_csum_set++; + cflags |= RGE_TDEXTSTS_TCPCSUM; + } + if (m->m_pkthdr.csum_flags & CSUM_UDP) { + sc->sc_drv_stats.tx_offload_udp_csum_set++; + cflags |= RGE_TDEXTSTS_UDPCSUM; + } + } + + /* Set up hardware VLAN tagging */ + if (m->m_flags & M_VLANTAG) { + sc->sc_drv_stats.tx_offload_vlan_tag_set++; + cflags |= htole16(m->m_pkthdr.ether_vtag) | RGE_TDEXTSTS_VTAG; + } + + cur = idx; + for (i = 1; i < nsegs; i++) { + cur = RGE_NEXT_TX_DESC(cur); + + cmdsts = RGE_TDCMDSTS_OWN; + cmdsts |= seg[i].ds_len; + + if (cur == RGE_TX_LIST_CNT - 1) + cmdsts |= RGE_TDCMDSTS_EOR; + if (i == nsegs - 1) + cmdsts |= RGE_TDCMDSTS_EOF; + + /* + * Note: vendor driver puts wmb() after opts2/extsts, + * before opts1/status. + * + * See the other place I have this comment for more + * information. + */ + d = &q->q_tx.rge_tx_list[cur]; + d->rge_addr = htole64(seg[i].ds_addr); + d->rge_extsts = htole32(cflags); + wmb(); + d->rge_cmdsts = htole32(cmdsts); + } + + /* Update info of TX queue and descriptors. */ + txq->txq_mbuf = m; + txq->txq_descidx = cur; + + cmdsts = RGE_TDCMDSTS_SOF; + cmdsts |= seg[0].ds_len; + + if (idx == RGE_TX_LIST_CNT - 1) + cmdsts |= RGE_TDCMDSTS_EOR; + if (nsegs == 1) + cmdsts |= RGE_TDCMDSTS_EOF; + + /* + * Note: vendor driver puts wmb() after opts2/extsts, + * before opts1/status. + * + * It does this: + * - set rge_addr + * - set extsts + * - wmb + * - set status - at this point it's owned by the hardware + * + */ + d = &q->q_tx.rge_tx_list[idx]; + d->rge_addr = htole64(seg[0].ds_addr); + d->rge_extsts = htole32(cflags); + wmb(); + d->rge_cmdsts = htole32(cmdsts); + wmb(); + + if (cur >= idx) { + rge_tx_list_sync(sc, q, idx, nsegs, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } else { + rge_tx_list_sync(sc, q, idx, RGE_TX_LIST_CNT - idx, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + rge_tx_list_sync(sc, q, 0, cur + 1, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + } + + /* Transfer ownership of packet to the chip. */ + cmdsts |= RGE_TDCMDSTS_OWN; + rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_POSTWRITE); + d->rge_cmdsts = htole32(cmdsts); + rge_tx_list_sync(sc, q, idx, 1, BUS_DMASYNC_PREWRITE); + wmb(); + + return (nsegs); +} + +static int +rge_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct rge_softc *sc = if_getsoftc(ifp); + struct ifreq *ifr = (struct ifreq *)data; + int error = 0; + + switch (cmd) { + case SIOCSIFMTU: + /* Note: no hardware reinit is required */ + if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > RGE_JUMBO_MTU) { + error = EINVAL; + break; + } + if (if_getmtu(ifp) != ifr->ifr_mtu) + if_setmtu(ifp, ifr->ifr_mtu); + + VLAN_CAPABILITIES(ifp); + break; + + case SIOCSIFFLAGS: + RGE_LOCK(sc); + if ((if_getflags(ifp) & IFF_UP) != 0) { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { + /* + * TODO: handle promisc/iffmulti changing + * without reprogramming everything. + */ + rge_init_locked(sc); + } else { + /* Reinit promisc/multi just in case */ + rge_iff_locked(sc); + } + } else { + if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { + rge_stop_locked(sc); + } + } + RGE_UNLOCK(sc); + break; + case SIOCADDMULTI: + case SIOCDELMULTI: + RGE_LOCK(sc); + if ((if_getflags(ifp) & IFF_DRV_RUNNING) != 0) { + rge_iff_locked(sc); + } + RGE_UNLOCK(sc); + break; + case SIOCGIFMEDIA: + case SIOCSIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &sc->sc_media, cmd); + break; + case SIOCSIFCAP: + { + int mask; + bool reinit = false; + + /* Get the mask of changed bits */ + mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); + + /* + * Locked so we don't have a narrow window where frames + * are being processed with the updated flags but the + * hardware configuration hasn't yet changed. + */ + RGE_LOCK(sc); + + if ((mask & IFCAP_TXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_TXCSUM); + if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) + if_sethwassistbits(ifp, RGE_CSUM_FEATURES, 0); + else + if_sethwassistbits(ifp, 0, RGE_CSUM_FEATURES); + reinit = 1; + } + + if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && + (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { + if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); + reinit = 1; + } + + /* TODO: WOL */ + + if ((mask & IFCAP_RXCSUM) != 0 && + (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { + if_togglecapenable(ifp, IFCAP_RXCSUM); + reinit = 1; + } + + if (reinit && if_getdrvflags(ifp) & IFF_DRV_RUNNING) { + if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); + rge_init_locked(sc); + } + + RGE_UNLOCK(sc); + VLAN_CAPABILITIES(ifp); + } + break; + default: + error = ether_ioctl(ifp, cmd, data); + break; + } + + return (error); +} + +static void +rge_qflush_if(if_t ifp) +{ + struct rge_softc *sc = if_getsoftc(ifp); + + /* TODO: this should iterate over the TXQs */ + RGE_LOCK(sc); + rge_txq_flush_mbufs(sc); + RGE_UNLOCK(sc); +} + +/** + * @brief Transmit the given frame to the hardware. + * + * This routine is called by the network stack to send + * a frame to the device. + * + * For now we simply direct dispatch this frame to the + * hardware (and thus avoid maintaining our own internal + * queue) + */ +static int +rge_transmit_if(if_t ifp, struct mbuf *m) +{ + struct rge_softc *sc = if_getsoftc(ifp); + int ret; + + sc->sc_drv_stats.transmit_call_cnt++; + + RGE_LOCK(sc); + if (sc->sc_stopped == true) { + sc->sc_drv_stats.transmit_stopped_cnt++; + RGE_UNLOCK(sc); + return (ENETDOWN); /* TODO: better error? */ + } + + /* XXX again should be a per-TXQ thing */ + ret = mbufq_enqueue(&sc->sc_txq, m); + if (ret != 0) { + sc->sc_drv_stats.transmit_full_cnt++; + RGE_UNLOCK(sc); + return (ret); + } + RGE_UNLOCK(sc); + + /* mbuf is owned by the driver, schedule transmit */ + taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); + sc->sc_drv_stats.transmit_queued_cnt++; + + return (0); +} + +static void +rge_init_if(void *xsc) +{ + struct rge_softc *sc = xsc; + + RGE_LOCK(sc); + rge_init_locked(sc); + RGE_UNLOCK(sc); +} + +static void +rge_init_locked(struct rge_softc *sc) +{ + struct rge_queues *q = sc->sc_queues; + uint32_t rxconf, val; + int i, num_miti; + + RGE_ASSERT_LOCKED(sc); + + RGE_DPRINTF(sc, RGE_DEBUG_INIT, "%s: called!\n", __func__); + + /* Don't double-init the hardware */ + if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) != 0) { + /* + * Note: I'm leaving this disabled by default; however + * I'm leaving it in here so I can figure out what's + * causing this to be initialised both from the ioctl + * API and if_init() API. + */ +// RGE_PRINT_ERROR(sc, "%s: called whilst running?\n", __func__); + return; + } + + /* + * Bring the hardware down so we know it's in a good known + * state before we bring it up in a good known state. + */ + rge_stop_locked(sc); + + /* Set MAC address. */ + rge_set_macaddr(sc, if_getlladdr(sc->sc_ifp)); + + /* Initialize RX and TX descriptors lists. */ + rge_rx_list_init(q); + rge_tx_list_init(q); + + if (rge_chipinit(sc)) { + RGE_PRINT_ERROR(sc, "%s: ERROR: chip init fail!\n", __func__); + return; + } + + if (rge_phy_config(sc)) + return; + + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + RGE_CLRBIT_1(sc, 0xf1, 0x80); + rge_disable_aspm_clkreq(sc); + RGE_WRITE_2(sc, RGE_EEE_TXIDLE_TIMER, + RGE_JUMBO_MTU + ETHER_HDR_LEN + 32); + + /* Load the addresses of the RX and TX lists into the chip. */ + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_rx.rge_rx_list_paddr)); + RGE_WRITE_4(sc, RGE_RXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_rx.rge_rx_list_paddr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_LO, + RGE_ADDR_LO(q->q_tx.rge_tx_list_paddr)); + RGE_WRITE_4(sc, RGE_TXDESC_ADDR_HI, + RGE_ADDR_HI(q->q_tx.rge_tx_list_paddr)); + + /* Set the initial RX and TX configurations. */ + if (sc->rge_type == MAC_R25) + rxconf = RGE_RXCFG_CONFIG; + else if (sc->rge_type == MAC_R25B) + rxconf = RGE_RXCFG_CONFIG_8125B; + else if (sc->rge_type == MAC_R25D) + rxconf = RGE_RXCFG_CONFIG_8125D; + else + rxconf = RGE_RXCFG_CONFIG_8126; + RGE_WRITE_4(sc, RGE_RXCFG, rxconf); + RGE_WRITE_4(sc, RGE_TXCFG, RGE_TXCFG_CONFIG); + + val = rge_read_csi(sc, 0x70c) & ~0x3f000000; + rge_write_csi(sc, 0x70c, val | 0x27000000); + + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) { + /* Disable L1 timeout. */ + val = rge_read_csi(sc, 0x890) & ~0x00000001; + rge_write_csi(sc, 0x890, val); + } else if (sc->rge_type != MAC_R25D) + RGE_WRITE_2(sc, 0x0382, 0x221b); + + RGE_WRITE_1(sc, RGE_RSS_CTRL, 0); + + val = RGE_READ_2(sc, RGE_RXQUEUE_CTRL) & ~0x001c; + RGE_WRITE_2(sc, RGE_RXQUEUE_CTRL, val | (fls(sc->sc_nqueues) - 1) << 2); + + RGE_CLRBIT_1(sc, RGE_CFG1, RGE_CFG1_SPEED_DOWN); + + rge_write_mac_ocp(sc, 0xc140, 0xffff); + rge_write_mac_ocp(sc, 0xc142, 0xffff); + + RGE_MAC_SETBIT(sc, 0xeb58, 0x0001); + + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) { + RGE_CLRBIT_1(sc, 0xd8, 0x02); + if (sc->rge_type == MAC_R27) { + RGE_CLRBIT_1(sc, 0x20e4, 0x04); + RGE_MAC_CLRBIT(sc, 0xe00c, 0x1000); + RGE_MAC_CLRBIT(sc, 0xc0c2, 0x0040); + } + } + + val = rge_read_mac_ocp(sc, 0xe614); + val &= (sc->rge_type == MAC_R27) ? ~0x0f00 : ~0x0700; + if (sc->rge_type == MAC_R25 || sc->rge_type == MAC_R25D) + rge_write_mac_ocp(sc, 0xe614, val | 0x0300); + else if (sc->rge_type == MAC_R25B) + rge_write_mac_ocp(sc, 0xe614, val | 0x0200); + else if (sc->rge_type == MAC_R26) + rge_write_mac_ocp(sc, 0xe614, val | 0x0300); + else + rge_write_mac_ocp(sc, 0xe614, val | 0x0f00); + + val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0c00; + rge_write_mac_ocp(sc, 0xe63e, val | + ((fls(sc->sc_nqueues) - 1) & 0x03) << 10); + + val = rge_read_mac_ocp(sc, 0xe63e) & ~0x0030; + rge_write_mac_ocp(sc, 0xe63e, val | 0x0020); + + RGE_MAC_CLRBIT(sc, 0xc0b4, 0x0001); + RGE_MAC_SETBIT(sc, 0xc0b4, 0x0001); + + RGE_MAC_SETBIT(sc, 0xc0b4, 0x000c); + + val = rge_read_mac_ocp(sc, 0xeb6a) & ~0x00ff; + rge_write_mac_ocp(sc, 0xeb6a, val | 0x0033); + + val = rge_read_mac_ocp(sc, 0xeb50) & ~0x03e0; + rge_write_mac_ocp(sc, 0xeb50, val | 0x0040); + + RGE_MAC_CLRBIT(sc, 0xe056, 0x00f0); + + RGE_WRITE_1(sc, RGE_TDFNR, 0x10); + + RGE_MAC_CLRBIT(sc, 0xe040, 0x1000); + + val = rge_read_mac_ocp(sc, 0xea1c) & ~0x0003; + rge_write_mac_ocp(sc, 0xea1c, val | 0x0001); + + if (sc->rge_type == MAC_R25D) + rge_write_mac_ocp(sc, 0xe0c0, 0x4403); + else + rge_write_mac_ocp(sc, 0xe0c0, 0x4000); + + RGE_MAC_SETBIT(sc, 0xe052, 0x0060); + RGE_MAC_CLRBIT(sc, 0xe052, 0x0088); + + val = rge_read_mac_ocp(sc, 0xd430) & ~0x0fff; + rge_write_mac_ocp(sc, 0xd430, val | 0x045f); + + RGE_SETBIT_1(sc, RGE_DLLPR, RGE_DLLPR_PFM_EN | RGE_DLLPR_TX_10M_PS_EN); + + if (sc->rge_type == MAC_R25) + RGE_SETBIT_1(sc, RGE_MCUCMD, 0x01); + + if (sc->rge_type != MAC_R25D) { + /* Disable EEE plus. */ + RGE_MAC_CLRBIT(sc, 0xe080, 0x0002); + } + + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) + RGE_MAC_CLRBIT(sc, 0xea1c, 0x0304); + else + RGE_MAC_CLRBIT(sc, 0xea1c, 0x0004); + + /* Clear tcam entries. */ + RGE_MAC_SETBIT(sc, 0xeb54, 0x0001); + DELAY(1); + RGE_MAC_CLRBIT(sc, 0xeb54, 0x0001); + + RGE_CLRBIT_2(sc, 0x1880, 0x0030); + + if (sc->rge_type == MAC_R27) { + val = rge_read_mac_ocp(sc, 0xd40c) & ~0xe038; + rge_write_phy_ocp(sc, 0xd40c, val | 0x8020); + } + + /* Config interrupt type. */ + if (sc->rge_type == MAC_R27) + RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_AVOID_MISS_INTR); + else if (sc->rge_type != MAC_R25) + RGE_CLRBIT_1(sc, RGE_INT_CFG0, RGE_INT_CFG0_EN); + + /* Clear timer interrupts. */ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + RGE_WRITE_4(sc, RGE_TIMERINT1, 0); + RGE_WRITE_4(sc, RGE_TIMERINT2, 0); + RGE_WRITE_4(sc, RGE_TIMERINT3, 0); + + num_miti = + (sc->rge_type == MAC_R25B || sc->rge_type == MAC_R26) ? 32 : 64; + /* Clear interrupt moderation timer. */ + for (i = 0; i < num_miti; i++) + RGE_WRITE_4(sc, RGE_INTMITI(i), 0); + + if (sc->rge_type == MAC_R26) { + RGE_CLRBIT_1(sc, RGE_INT_CFG0, + RGE_INT_CFG0_TIMEOUT_BYPASS | RGE_INT_CFG0_RDU_BYPASS_8126 | + RGE_INT_CFG0_MITIGATION_BYPASS); + RGE_WRITE_2(sc, RGE_INT_CFG1, 0); + } + + RGE_MAC_SETBIT(sc, 0xc0ac, 0x1f80); + + rge_write_mac_ocp(sc, 0xe098, 0xc302); + + RGE_MAC_CLRBIT(sc, 0xe032, 0x0003); + val = rge_read_csi(sc, 0x98) & ~0x0000ff00; + rge_write_csi(sc, 0x98, val); + + if (sc->rge_type == MAC_R25D) { + val = rge_read_mac_ocp(sc, 0xe092) & ~0x00ff; + rge_write_mac_ocp(sc, 0xe092, val | 0x0008); + } else + RGE_MAC_CLRBIT(sc, 0xe092, 0x00ff); + + /* Enable/disable HW VLAN tagging based on enabled capability */ + if ((if_getcapabilities(sc->sc_ifp) & IFCAP_VLAN_HWTAGGING) != 0) + RGE_SETBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); + else + RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_VLANSTRIP); + + /* Enable/disable RX checksum based on enabled capability */ + if ((if_getcapenable(sc->sc_ifp) & IFCAP_RXCSUM) != 0) + RGE_SETBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM); + else + RGE_CLRBIT_2(sc, RGE_CPLUSCMD, RGE_CPLUSCMD_RXCSUM); + RGE_READ_2(sc, RGE_CPLUSCMD); + + /* Set Maximum frame size. */ + RGE_WRITE_2(sc, RGE_RXMAXSIZE, RGE_JUMBO_FRAMELEN); + + /* Disable RXDV gate. */ + RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); + DELAY(2000); + + /* Program promiscuous mode and multicast filters. */ + rge_iff_locked(sc); + + if (sc->rge_type == MAC_R27) + RGE_CLRBIT_1(sc, RGE_RADMFIFO_PROTECT, 0x2001); + + rge_disable_aspm_clkreq(sc); + + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + DELAY(10); + + rge_ifmedia_upd(sc->sc_ifp); + + /* Enable transmit and receive. */ + RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_TXENB | RGE_CMD_RXENB); + + /* Enable interrupts. */ + rge_setup_intr(sc, RGE_IMTYPE_SIM); + + if_setdrvflagbits(sc->sc_ifp, IFF_DRV_RUNNING, 0); + if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_OACTIVE); + + callout_reset(&sc->sc_timeout, hz, rge_tick, sc); + + RGE_DPRINTF(sc, RGE_DEBUG_INIT, "%s: init completed!\n", __func__); + + /* Unblock transmit when we release the lock */ + sc->sc_stopped = false; +} + +/* + * @brief Stop the adapter and free any mbufs allocated to the RX and TX lists. + * + * Must be called with the driver lock held. + */ +void +rge_stop_locked(struct rge_softc *sc) +{ + struct rge_queues *q = sc->sc_queues; + int i; + + RGE_ASSERT_LOCKED(sc); + + RGE_DPRINTF(sc, RGE_DEBUG_INIT, "%s: called!\n", __func__); + + callout_stop(&sc->sc_timeout); + + /* Stop pending TX submissions */ + sc->sc_stopped = true; + + if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_RUNNING); + sc->rge_timerintr = 0; + sc->sc_watchdog = 0; + + RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | + RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | + RGE_RXCFG_ERRPKT); + + rge_hw_reset(sc); + + RGE_MAC_CLRBIT(sc, 0xc0ac, 0x1f80); + + if_setdrvflagbits(sc->sc_ifp, 0, IFF_DRV_OACTIVE); + + if (q->q_rx.rge_head != NULL) { + m_freem(q->q_rx.rge_head); + q->q_rx.rge_head = NULL; + q->q_rx.rge_tail = &q->q_rx.rge_head; + } + + /* Free the TX list buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + if (q->q_tx.rge_txq[i].txq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat_tx_buf, + q->q_tx.rge_txq[i].txq_dmamap); + m_freem(q->q_tx.rge_txq[i].txq_mbuf); + q->q_tx.rge_txq[i].txq_mbuf = NULL; + } + } + + /* Free the RX list buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + if (q->q_rx.rge_rxq[i].rxq_mbuf != NULL) { + bus_dmamap_unload(sc->sc_dmat_rx_buf, + q->q_rx.rge_rxq[i].rxq_dmamap); + m_freem(q->q_rx.rge_rxq[i].rxq_mbuf); + q->q_rx.rge_rxq[i].rxq_mbuf = NULL; + } + } + + /* Free pending TX frames */ + /* TODO: should be per TX queue */ + rge_txq_flush_mbufs(sc); +} + +/* + * Set media options. + */ +static int +rge_ifmedia_upd(if_t ifp) +{ + struct rge_softc *sc = if_getsoftc(ifp); + struct ifmedia *ifm = &sc->sc_media; + int anar, gig, val; + + if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) + return (EINVAL); + + /* Disable Gigabit Lite. */ + RGE_PHY_CLRBIT(sc, 0xa428, 0x0200); + RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0001); + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) + RGE_PHY_CLRBIT(sc, 0xa5ea, 0x0007); + + val = rge_read_phy_ocp(sc, 0xa5d4); + switch (sc->rge_type) { + case MAC_R27: + val &= ~RGE_ADV_10000TFDX; + /* fallthrough */ + case MAC_R26: + val &= ~RGE_ADV_5000TFDX; + /* fallthrough */ + default: + val &= ~RGE_ADV_2500TFDX; + break; + } + + anar = ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10; + gig = GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX; + + switch (IFM_SUBTYPE(ifm->ifm_media)) { + case IFM_AUTO: + val |= RGE_ADV_2500TFDX; + if (sc->rge_type == MAC_R26) + val |= RGE_ADV_5000TFDX; + else if (sc->rge_type == MAC_R27) + val |= RGE_ADV_5000TFDX | RGE_ADV_10000TFDX; + break; + case IFM_10G_T: + val |= RGE_ADV_10000TFDX; + if_setbaudrate(ifp, IF_Gbps(10)); + break; + case IFM_5000_T: + val |= RGE_ADV_5000TFDX; + if_setbaudrate(ifp, IF_Gbps(5)); + break; + case IFM_2500_T: + val |= RGE_ADV_2500TFDX; + if_setbaudrate(ifp, IF_Mbps(2500)); + break; + case IFM_1000_T: + if_setbaudrate(ifp, IF_Gbps(1)); + break; + case IFM_100_TX: + gig = rge_read_phy(sc, 0, MII_100T2CR) & + ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); + anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? + ANAR_TX | ANAR_TX_FD | ANAR_10_FD | ANAR_10 : + ANAR_TX | ANAR_10_FD | ANAR_10; + if_setbaudrate(ifp, IF_Mbps(100)); + break; + case IFM_10_T: + gig = rge_read_phy(sc, 0, MII_100T2CR) & + ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX); + anar = ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) ? + ANAR_10_FD | ANAR_10 : ANAR_10; + if_setbaudrate(ifp, IF_Mbps(10)); + break; + default: + RGE_PRINT_ERROR(sc, "unsupported media type\n"); + return (EINVAL); + } + + rge_write_phy(sc, 0, MII_ANAR, anar | ANAR_PAUSE_ASYM | ANAR_FC); + rge_write_phy(sc, 0, MII_100T2CR, gig); + rge_write_phy_ocp(sc, 0xa5d4, val); + rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | + BMCR_STARTNEG); + + return (0); +} + +/* + * Report current media status. + */ +static void +rge_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) +{ + struct rge_softc *sc = if_getsoftc(ifp); + uint16_t status = 0; + + ifmr->ifm_status = IFM_AVALID; + ifmr->ifm_active = IFM_ETHER; + + if (rge_get_link_status(sc)) { + ifmr->ifm_status |= IFM_ACTIVE; + + status = RGE_READ_2(sc, RGE_PHYSTAT); + if ((status & RGE_PHYSTAT_FDX) || + (status & (RGE_PHYSTAT_1000MBPS | RGE_PHYSTAT_2500MBPS | + RGE_PHYSTAT_5000MBPS | RGE_PHYSTAT_10000MBPS))) + ifmr->ifm_active |= IFM_FDX; + else + ifmr->ifm_active |= IFM_HDX; + + if (status & RGE_PHYSTAT_10MBPS) + ifmr->ifm_active |= IFM_10_T; + else if (status & RGE_PHYSTAT_100MBPS) + ifmr->ifm_active |= IFM_100_TX; + else if (status & RGE_PHYSTAT_1000MBPS) + ifmr->ifm_active |= IFM_1000_T; + else if (status & RGE_PHYSTAT_2500MBPS) + ifmr->ifm_active |= IFM_2500_T; + else if (status & RGE_PHYSTAT_5000MBPS) + ifmr->ifm_active |= IFM_5000_T; + else if (status & RGE_PHYSTAT_5000MBPS) + ifmr->ifm_active |= IFM_5000_T; + else if (status & RGE_PHYSTAT_10000MBPS) + ifmr->ifm_active |= IFM_10G_T; + } +} + +/** + * @brief callback to load/populate a single physical address + */ +static void +rge_dma_load_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) +{ + bus_addr_t *paddr = (bus_addr_t *) arg; + + *paddr = 0; + + if (error) { + printf("%s: error! (%d)\n", __func__, error); + *paddr = 0; + return; + } + + if (nsegs != 1) { + printf("%s: too many segs (got %d)\n", __func__, nsegs); + *paddr = 0; + return; + } + + *paddr = segs[0].ds_addr; +} + +/** + * @brief Allocate memory for RX/TX rings. + * + * Called with the driver lock NOT held. + */ +static int +rge_allocmem(struct rge_softc *sc) +{ + struct rge_queues *q = sc->sc_queues; + int error; + int i; + + RGE_ASSERT_UNLOCKED(sc); + + /* Allocate DMA'able memory for the TX ring. */ + error = bus_dmamem_alloc(sc->sc_dmat_tx_desc, + (void **) &q->q_tx.rge_tx_list, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &q->q_tx.rge_tx_list_map); + if (error) { + RGE_PRINT_ERROR(sc, "%s: error (alloc tx_list.map) (%d)\n", + __func__, error); + goto error; + } + + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: tx_list=%p\n", __func__, + q->q_tx.rge_tx_list); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: tx_list_map=%p\n", __func__, + q->q_tx.rge_tx_list_map); + + /* Load the map for the TX ring. */ + error = bus_dmamap_load(sc->sc_dmat_tx_desc, + q->q_tx.rge_tx_list_map, + q->q_tx.rge_tx_list, + RGE_TX_LIST_SZ, + rge_dma_load_cb, + (void *) &q->q_tx.rge_tx_list_paddr, + BUS_DMA_NOWAIT); + + if ((error != 0) || (q->q_tx.rge_tx_list_paddr == 0)) { + RGE_PRINT_ERROR(sc, "%s: error (load tx_list.map) (%d)\n", + __func__, error); + goto error; + } + + /* Create DMA maps for TX buffers. */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat_tx_buf, + 0, &q->q_tx.rge_txq[i].txq_dmamap); + if (error) { + RGE_PRINT_ERROR(sc, + "can't create DMA map for TX (%d)\n", error); + goto error; + } + } + + /* Allocate DMA'able memory for the RX ring. */ + error = bus_dmamem_alloc(sc->sc_dmat_rx_desc, + (void **) &q->q_rx.rge_rx_list, + BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, + &q->q_rx.rge_rx_list_map); + if (error) { + RGE_PRINT_ERROR(sc, "%s: error (alloc rx_list.map) (%d)\n", + __func__, error); + goto error; + } + + RGE_DPRINTF(sc, RGE_DEBUG_INIT, "%s: rx_list=%p\n", __func__, + q->q_rx.rge_rx_list); + RGE_DPRINTF(sc, RGE_DEBUG_INIT, "%s: rx_list_map=%p\n", __func__, + q->q_rx.rge_rx_list_map); + + /* Load the map for the RX ring. */ + error = bus_dmamap_load(sc->sc_dmat_rx_desc, + q->q_rx.rge_rx_list_map, + q->q_rx.rge_rx_list, + RGE_RX_LIST_SZ, + rge_dma_load_cb, + (void *) &q->q_rx.rge_rx_list_paddr, + BUS_DMA_NOWAIT); + + if ((error != 0) || (q->q_rx.rge_rx_list_paddr == 0)) { + RGE_PRINT_ERROR(sc, "%s: error (load rx_list.map) (%d)\n", + __func__, error); + goto error; + } + + /* Create DMA maps for RX buffers. */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + error = bus_dmamap_create(sc->sc_dmat_rx_buf, + 0, &q->q_rx.rge_rxq[i].rxq_dmamap); + if (error) { + RGE_PRINT_ERROR(sc, + "can't create DMA map for RX (%d)\n", error); + goto error; + } + } + + return (0); +error: + + rge_freemem(sc); + + return (error); +} + +/** + * @brief Allocate memory for MAC stats. + * + * Called with the driver lock NOT held. + */ +static int +rge_alloc_stats_mem(struct rge_softc *sc) +{ + struct rge_mac_stats *ss = &sc->sc_mac_stats; + int error; + + RGE_ASSERT_UNLOCKED(sc); + + /* Allocate DMA'able memory for the stats buffer. */ + error = bus_dmamem_alloc(sc->sc_dmat_stats_buf, + (void **) &ss->stats, BUS_DMA_WAITOK | BUS_DMA_ZERO, + &ss->map); + if (error) { + RGE_PRINT_ERROR(sc, "%s: error (alloc stats) (%d)\n", + __func__, error); + goto error; + } + + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: stats=%p\n", __func__, ss->stats); + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: map=%p\n", __func__, ss->map); + + /* Load the map for the TX ring. */ + error = bus_dmamap_load(sc->sc_dmat_stats_buf, + ss->map, + ss->stats, + RGE_STATS_BUF_SIZE, + rge_dma_load_cb, + (void *) &ss->paddr, + BUS_DMA_NOWAIT); + + if ((error != 0) || (ss->paddr == 0)) { + RGE_PRINT_ERROR(sc, "%s: error (load stats.map) (%d)\n", + __func__, error); + if (error == 0) + error = ENXIO; + goto error; + } + + return (0); + +error: + rge_free_stats_mem(sc); + + return (error); +} + + +/** + * @brief Free the TX/RX DMA buffers and mbufs. + * + * Called with the driver lock NOT held. + */ +static int +rge_freemem(struct rge_softc *sc) +{ + struct rge_queues *q = sc->sc_queues; + int i; + + RGE_ASSERT_UNLOCKED(sc); + + /* TX desc */ + bus_dmamap_unload(sc->sc_dmat_tx_desc, q->q_tx.rge_tx_list_map); + if (q->q_tx.rge_tx_list != NULL) + bus_dmamem_free(sc->sc_dmat_tx_desc, q->q_tx.rge_tx_list, + q->q_tx.rge_tx_list_map); + memset(&q->q_tx, 0, sizeof(q->q_tx)); + + /* TX buf */ + for (i = 0; i < RGE_TX_LIST_CNT; i++) { + struct rge_txq *tx = &q->q_tx.rge_txq[i]; + + /* unmap/free mbuf if it's still alloc'ed and mapped */ + if (tx->txq_mbuf != NULL) { + static bool do_warning = false; + + if (do_warning == false) { + RGE_PRINT_ERROR(sc, + "%s: TX mbuf should've been freed!\n", + __func__); + do_warning = true; + } + if (tx->txq_dmamap != NULL) { + bus_dmamap_sync(sc->sc_dmat_tx_buf, + tx->txq_dmamap, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sc_dmat_tx_buf, + tx->txq_dmamap); + } + m_free(tx->txq_mbuf); + tx->txq_mbuf = NULL; + } + + /* Destroy the dmamap if it's allocated */ + if (tx->txq_dmamap != NULL) { + bus_dmamap_destroy(sc->sc_dmat_tx_buf, tx->txq_dmamap); + tx->txq_dmamap = NULL; + } + } + + /* RX desc */ + bus_dmamap_unload(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list_map); + if (q->q_rx.rge_rx_list != 0) + bus_dmamem_free(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list, + q->q_rx.rge_rx_list_map); + memset(&q->q_rx, 0, sizeof(q->q_tx)); + + /* RX buf */ + for (i = 0; i < RGE_RX_LIST_CNT; i++) { + struct rge_rxq *rx = &q->q_rx.rge_rxq[i]; + + /* unmap/free mbuf if it's still alloc'ed and mapped */ + if (rx->rxq_mbuf != NULL) { + if (rx->rxq_dmamap != NULL) { + bus_dmamap_sync(sc->sc_dmat_rx_buf, + rx->rxq_dmamap, BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->sc_dmat_rx_buf, + rx->rxq_dmamap); + } + m_free(rx->rxq_mbuf); + rx->rxq_mbuf = NULL; + } + + /* Destroy the dmamap if it's allocated */ + if (rx->rxq_dmamap != NULL) { + bus_dmamap_destroy(sc->sc_dmat_rx_buf, rx->rxq_dmamap); + rx->rxq_dmamap = NULL; + } + } + + return (0); +} + +/** + * @brief Free the stats memory. + * + * Called with the driver lock NOT held. + */ +static int +rge_free_stats_mem(struct rge_softc *sc) +{ + struct rge_mac_stats *ss = &sc->sc_mac_stats; + + RGE_ASSERT_UNLOCKED(sc); + + bus_dmamap_unload(sc->sc_dmat_stats_buf, ss->map); + if (ss->stats != NULL) + bus_dmamem_free(sc->sc_dmat_stats_buf, ss->stats, ss->map); + memset(ss, 0, sizeof(*ss)); + return (0); +} + +static uint32_t +rx_ring_space(struct rge_queues *q) +{ + uint32_t prod, cons; + uint32_t ret; + + RGE_ASSERT_LOCKED(q->q_sc); + + prod = q->q_rx.rge_rxq_prodidx; + cons = q->q_rx.rge_rxq_considx; + + ret = (cons + RGE_RX_LIST_CNT - prod - 1) % RGE_RX_LIST_CNT + 1; + + if (ret > RGE_RX_LIST_CNT) + return RGE_RX_LIST_CNT; + + return (ret); +} + +/* + * Initialize the RX descriptor and attach an mbuf cluster at the given offset. + * + * Note: this relies on the rxr ring buffer abstraction to not + * over-fill the RX ring. For FreeBSD we'll need to use the + * prod/cons RX indexes to know how much RX ring space to + * populate. + * + * This routine will increment the producer index if successful. + * + * This must be called with the driver lock held. + */ +static int +rge_newbuf(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct mbuf *m; + struct rge_rx_desc *r; + struct rge_rxq *rxq; + bus_dmamap_t rxmap; + bus_dma_segment_t seg[1]; + uint32_t cmdsts; + int nsegs; + uint32_t idx; + + RGE_ASSERT_LOCKED(q->q_sc); + + /* + * Verify we have enough space in the ring; error out + * if we do not. + */ + if (rx_ring_space(q) == 0) + return (ENOBUFS); + + idx = q->q_rx.rge_rxq_prodidx; + rxq = &q->q_rx.rge_rxq[idx]; + rxmap = rxq->rxq_dmamap; + + /* + * If we already have an mbuf here then something messed up; + * exit out as the hardware may be DMAing to it. + */ + if (rxq->rxq_mbuf != NULL) { + RGE_PRINT_ERROR(sc, + "%s: RX ring slot %d already has an mbuf?\n", __func__, + idx); + return (ENOBUFS); + } + + /* Allocate single buffer backed mbuf of MCLBYTES */ + m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); + if (m == NULL) + return (ENOBUFS); + + m->m_len = m->m_pkthdr.len = MCLBYTES; + + nsegs = 1; + if (bus_dmamap_load_mbuf_sg(sc->sc_dmat_rx_buf, rxmap, m, seg, &nsegs, + BUS_DMA_NOWAIT)) { + m_freem(m); + return (ENOBUFS); + } + + /* + * Make sure any changes made to the buffer have been flushed to host + * memory. + */ + bus_dmamap_sync(sc->sc_dmat_rx_buf, rxmap, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + + /* + * Map the segment into RX descriptors. Note that this + * only currently supports a single segment per mbuf; + * the call to load_mbuf_sg above specified a single segment. + */ + r = &q->q_rx.rge_rx_list[idx]; + + rxq->rxq_mbuf = m; + + cmdsts = seg[0].ds_len; /* XXX how big is this field in the descriptor? */ + if (idx == RGE_RX_LIST_CNT - 1) + cmdsts |= RGE_RDCMDSTS_EOR; + + /* + * Configure the DMA pointer and config, but don't hand + * it yet to the hardware. + */ + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); + r->hi_qword1.rx_qword4.rge_extsts = htole32(0); + r->hi_qword0.rge_addr = htole64(seg[0].ds_addr); + wmb(); + + /* + * Mark the specific descriptor slot as "this descriptor is now + * owned by the hardware", which when the hardware next sees + * this, it'll continue RX DMA. + */ + cmdsts |= RGE_RDCMDSTS_OWN; + r->hi_qword1.rx_qword4.rge_cmdsts = htole32(cmdsts); + wmb(); + + /* + * At this point the hope is the whole ring is now updated and + * consistent; if the hardware was waiting for a descriptor to be + * ready to write into then it should be ready here. + */ + + RGE_DPRINTF(sc, RGE_DEBUG_RECV_DESC, + "%s: [%d]: m=%p, m_data=%p, m_len=%ju, phys=0x%jx len %ju, " + "desc=0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + __func__, + idx, + m, + m->m_data, + (uintmax_t) m->m_len, + (uintmax_t) seg[0].ds_addr, + (uintmax_t) seg[0].ds_len, + ((uint32_t *) r)[0], + ((uint32_t *) r)[1], + ((uint32_t *) r)[2], + ((uint32_t *) r)[3], + ((uint32_t *) r)[4], + ((uint32_t *) r)[5], + ((uint32_t *) r)[6], + ((uint32_t *) r)[7]); + + q->q_rx.rge_rxq_prodidx = RGE_NEXT_RX_DESC(idx); + + return (0); +} + +static void +rge_rx_list_init(struct rge_queues *q) +{ + memset(q->q_rx.rge_rx_list, 0, RGE_RX_LIST_SZ); + + RGE_ASSERT_LOCKED(q->q_sc); + + q->q_rx.rge_rxq_prodidx = q->q_rx.rge_rxq_considx = 0; + q->q_rx.rge_head = NULL; + q->q_rx.rge_tail = &q->q_rx.rge_head; + + RGE_DPRINTF(q->q_sc, RGE_DEBUG_SETUP, "%s: rx_list=%p\n", __func__, + q->q_rx.rge_rx_list); + + rge_fill_rx_ring(q); +} + +/** + * @brief Fill / refill the RX ring as needed. + * + * Refill the RX ring with one less than the total descriptors needed. + * This makes the check in rge_rxeof() easier - it can just check + * descriptors from cons -> prod and bail once it hits prod. + * If the whole ring is filled then cons == prod, and that shortcut + * fails. + * + * This must be called with the driver lock held. + */ +static void +rge_fill_rx_ring(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + uint32_t count, i, prod, cons; + + RGE_ASSERT_LOCKED(q->q_sc); + + prod = q->q_rx.rge_rxq_prodidx; + cons = q->q_rx.rge_rxq_considx; + count = rx_ring_space(q); + + /* Fill to count-1; bail if we don't have the space */ + if (count <= 1) + return; + count--; + + RGE_DPRINTF(sc, RGE_DEBUG_RECV_DESC, "%s: prod=%u, cons=%u, space=%u\n", + __func__, prod, cons, count); + + /* Make sure device->host changes are visible */ + bus_dmamap_sync(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + for (i = 0; i < count; i++) { + if (rge_newbuf(q)) + break; + } + + /* Make changes visible to the device */ + bus_dmamap_sync(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list_map, + BUS_DMASYNC_PREWRITE); +} + +static void +rge_tx_list_init(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct rge_tx_desc *d; + int i; + + RGE_ASSERT_LOCKED(q->q_sc); + + memset(q->q_tx.rge_tx_list, 0, RGE_TX_LIST_SZ); + + for (i = 0; i < RGE_TX_LIST_CNT; i++) + q->q_tx.rge_txq[i].txq_mbuf = NULL; + + d = &q->q_tx.rge_tx_list[RGE_TX_LIST_CNT - 1]; + d->rge_cmdsts = htole32(RGE_TDCMDSTS_EOR); + + bus_dmamap_sync(sc->sc_dmat_tx_desc, q->q_tx.rge_tx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + wmb(); + + q->q_tx.rge_txq_prodidx = q->q_tx.rge_txq_considx = 0; + + RGE_DPRINTF(sc, RGE_DEBUG_SETUP, "%s: rx_list=%p\n", __func__, + q->q_tx.rge_tx_list); +} + +int +rge_rxeof(struct rge_queues *q, struct mbufq *mq) +{ + struct rge_softc *sc = q->q_sc; + struct mbuf *m; + struct rge_rx_desc *cur_rx; + struct rge_rxq *rxq; + uint32_t rxstat, extsts; + int i, mlen, rx = 0; + int cons, prod; + int maxpkt = 16; /* XXX TODO: make this a tunable */ + bool check_hwcsum; + + check_hwcsum = ((if_getcapenable(sc->sc_ifp) & IFCAP_RXCSUM) != 0); + + RGE_ASSERT_LOCKED(sc); + + sc->sc_drv_stats.rxeof_cnt++; + + RGE_DPRINTF(sc, RGE_DEBUG_INTR, "%s; called\n", __func__); + + /* Note: if_re is POSTREAD/WRITE, rge is only POSTWRITE */ + bus_dmamap_sync(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list_map, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + + prod = q->q_rx.rge_rxq_prodidx; + + /* + * Loop around until we've run out of active descriptors to check + * or maxpkt has been reached. + */ + for (i = cons = q->q_rx.rge_rxq_considx; + maxpkt > 0 && i != prod; + i = RGE_NEXT_RX_DESC(i)) { + /* break out of loop if we're not running */ + if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) == 0) + break; + + /* get the current rx descriptor to check descriptor status */ + cur_rx = &q->q_rx.rge_rx_list[i]; + rxstat = le32toh(cur_rx->hi_qword1.rx_qword4.rge_cmdsts); + if ((rxstat & RGE_RDCMDSTS_OWN) != 0) { + break; + } + + /* Ensure everything else has been DMAed */ + rmb(); + + /* Get the current rx buffer, sync */ + rxq = &q->q_rx.rge_rxq[i]; + + /* Ensure any device updates are now visible in host memory */ + bus_dmamap_sync(sc->sc_dmat_rx_buf, rxq->rxq_dmamap, + BUS_DMASYNC_POSTREAD); + + /* Unload the DMA map, we are done with it here */ + bus_dmamap_unload(sc->sc_dmat_rx_buf, rxq->rxq_dmamap); + m = rxq->rxq_mbuf; + rxq->rxq_mbuf = NULL; + + rx = 1; + + RGE_DPRINTF(sc, RGE_DEBUG_RECV_DESC, + "%s: RX: [%d]: m=%p, m_data=%p, m_len=%ju, " + "desc=0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", + __func__, + i, + m, + m->m_data, + (uintmax_t) m->m_len, + ((uint32_t *) cur_rx)[0], + ((uint32_t *) cur_rx)[1], + ((uint32_t *) cur_rx)[2], + ((uint32_t *) cur_rx)[3], + ((uint32_t *) cur_rx)[4], + ((uint32_t *) cur_rx)[5], + ((uint32_t *) cur_rx)[6], + ((uint32_t *) cur_rx)[7]); + + if ((rxstat & RGE_RDCMDSTS_SOF) != 0) { + if (q->q_rx.rge_head != NULL) { + sc->sc_drv_stats.rx_desc_err_multidesc++; + if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, + 1); + m_freem(q->q_rx.rge_head); + q->q_rx.rge_tail = &q->q_rx.rge_head; + } + + m->m_pkthdr.len = 0; + } else if (q->q_rx.rge_head == NULL) { + m_freem(m); + continue; + } else + m->m_flags &= ~M_PKTHDR; + + *q->q_rx.rge_tail = m; + q->q_rx.rge_tail = &m->m_next; + + mlen = rxstat & RGE_RDCMDSTS_FRAGLEN; + m->m_len = mlen; + + m = q->q_rx.rge_head; + m->m_pkthdr.len += mlen; + + /* Ethernet CRC error */ + if (rxstat & RGE_RDCMDSTS_RXERRSUM) { + sc->sc_drv_stats.rx_ether_csum_err++; + if_inc_counter(sc->sc_ifp, IFCOUNTER_IERRORS, 1); + m_freem(m); + q->q_rx.rge_head = NULL; + q->q_rx.rge_tail = &q->q_rx.rge_head; + continue; + } + + /* + * This mbuf is part of a multi-descriptor frame, + * so count it towards that. + * + * Yes, this means we won't be counting the + * final descriptor/mbuf as part of a multi-descriptor + * frame; if someone wishes to do that then it + * shouldn't be too hard to add. + */ + if ((rxstat & RGE_RDCMDSTS_EOF) == 0) { + sc->sc_drv_stats.rx_desc_jumbo_frag++; + continue; + } + + q->q_rx.rge_head = NULL; + q->q_rx.rge_tail = &q->q_rx.rge_head; + + m_adj(m, -ETHER_CRC_LEN); + m->m_pkthdr.rcvif = sc->sc_ifp; + if_inc_counter(sc->sc_ifp, IFCOUNTER_IPACKETS, 1); + + extsts = le32toh(cur_rx->hi_qword1.rx_qword4.rge_extsts); + + /* Check IP header checksum. */ + if (check_hwcsum) { + /* Does it exist for IPv4? */ + if (extsts & RGE_RDEXTSTS_IPV4) { + sc->sc_drv_stats.rx_offload_csum_ipv4_exists++; + m->m_pkthdr.csum_flags |= + CSUM_IP_CHECKED; + } + /* XXX IPv6 checksum check? */ + + if (((extsts & RGE_RDEXTSTS_IPCSUMERR) == 0) + && ((extsts & RGE_RDEXTSTS_IPV4) != 0)) { + sc->sc_drv_stats.rx_offload_csum_ipv4_valid++; + m->m_pkthdr.csum_flags |= + CSUM_IP_VALID; + } + + /* Check TCP/UDP checksum. */ + if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && + (extsts & RGE_RDEXTSTS_TCPPKT)) { + sc->sc_drv_stats.rx_offload_csum_tcp_exists++; + if ((extsts & RGE_RDEXTSTS_TCPCSUMERR) == 0) { + sc->sc_drv_stats.rx_offload_csum_tcp_valid++; + /* TCP checksum OK */ + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID|CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + + if ((extsts & (RGE_RDEXTSTS_IPV4 | RGE_RDEXTSTS_IPV6)) && + (extsts & RGE_RDEXTSTS_UDPPKT)) { + sc->sc_drv_stats.rx_offload_csum_udp_exists++; + if ((extsts & RGE_RDEXTSTS_UDPCSUMERR) == 0) { + sc->sc_drv_stats.rx_offload_csum_udp_valid++; + /* UDP checksum OK */ + m->m_pkthdr.csum_flags |= + CSUM_DATA_VALID|CSUM_PSEUDO_HDR; + m->m_pkthdr.csum_data = 0xffff; + } + } + } + + if (extsts & RGE_RDEXTSTS_VTAG) { + sc->sc_drv_stats.rx_offload_vlan_tag++; + m->m_pkthdr.ether_vtag = + ntohs(extsts & RGE_RDEXTSTS_VLAN_MASK); + m->m_flags |= M_VLANTAG; + } + + mbufq_enqueue(mq, m); + + maxpkt--; + } + + if (!rx) + return (0); + + /* + * Make sure any device updates to the descriptor ring are + * visible to the host before we continue. + */ + bus_dmamap_sync(sc->sc_dmat_rx_desc, q->q_rx.rge_rx_list_map, + BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); + wmb(); + + /* Update the consumer index, refill the RX ring */ + q->q_rx.rge_rxq_considx = i; + rge_fill_rx_ring(q); + + return (1); +} + +int +rge_txeof(struct rge_queues *q) +{ + struct rge_softc *sc = q->q_sc; + struct ifnet *ifp = sc->sc_ifp; + struct rge_txq *txq; + uint32_t txstat; + int cons, prod, cur, idx; + int free = 0, ntx = 0; + int pktlen; + bool is_mcast; + + RGE_ASSERT_LOCKED(sc); + + sc->sc_drv_stats.txeof_cnt++; + + prod = q->q_tx.rge_txq_prodidx; + cons = q->q_tx.rge_txq_considx; + + idx = cons; + while (idx != prod) { + txq = &q->q_tx.rge_txq[idx]; + cur = txq->txq_descidx; + + rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_POSTREAD); + txstat = q->q_tx.rge_tx_list[cur].rge_cmdsts; + rge_tx_list_sync(sc, q, cur, 1, BUS_DMASYNC_PREREAD); + if ((txstat & htole32(RGE_TDCMDSTS_OWN)) != 0) { + free = 2; + break; + } + + bus_dmamap_sync(sc->sc_dmat_tx_buf, txq->txq_dmamap, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->sc_dmat_tx_buf, txq->txq_dmamap); + pktlen = txq->txq_mbuf->m_pkthdr.len; + is_mcast = ((txq->txq_mbuf->m_flags & M_MCAST) != 0); + m_freem(txq->txq_mbuf); + txq->txq_mbuf = NULL; + ntx++; + + if ((txstat & + htole32(RGE_TDCMDSTS_EXCESSCOLL | RGE_TDCMDSTS_COLL)) != 0) + if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 1); + if ((txstat & htole32(RGE_TDCMDSTS_TXERR)) != 0) + if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); + else { + if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); + if_inc_counter(ifp, IFCOUNTER_OBYTES, pktlen); + if (is_mcast) + if_inc_counter(ifp, IFCOUNTER_OMCASTS, 1); + + } + + idx = RGE_NEXT_TX_DESC(cur); + free = 1; + } + + /* If we didn't complete any TX descriptors then return 0 */ + if (free == 0) + return (0); + + if (idx >= cons) { + rge_tx_list_sync(sc, q, cons, idx - cons, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + } else { + rge_tx_list_sync(sc, q, cons, RGE_TX_LIST_CNT - cons, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + rge_tx_list_sync(sc, q, 0, idx, + BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); + } + + q->q_tx.rge_txq_considx = idx; + + RGE_DPRINTF(sc, RGE_DEBUG_XMIT, + "%s: handled %d frames; prod=%d, cons=%d\n", __func__, + ntx, q->q_tx.rge_txq_prodidx, q->q_tx.rge_txq_considx); + + /* + * We processed the ring and hit a descriptor that was still + * owned by the hardware, so there's still pending work. + * + * If we got to the end of the ring and there's no further + * frames owned by the hardware then we can quieten the + * watchdog. + */ + if (free == 2) + sc->sc_watchdog = 5; + else + sc->sc_watchdog = 0; + + /* + * Kick-start the transmit task just in case we have + * more frames available. + */ + taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); + + return (1); +} + +static u_int +rge_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) +{ + uint32_t crc, *hashes = arg; + + // XXX TODO: validate this does addrlo? */ + crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN) >> 26; + crc &= 0x3f; + + if (crc < 32) + hashes[0] |= (1 << crc); + else + hashes[1] |= (1 << (crc - 32)); + + return (1); +} + +/** + * @brief Configure the RX filter and multicast filter. + * + * This must be called with the driver lock held. + */ +static void +rge_iff_locked(struct rge_softc *sc) +{ + uint32_t hashes[2]; + uint32_t rxfilt; + + RGE_ASSERT_LOCKED(sc); + + rxfilt = RGE_READ_4(sc, RGE_RXCFG); + rxfilt &= ~(RGE_RXCFG_ALLPHYS | RGE_RXCFG_MULTI); + + /* + * Always accept frames destined to our station address. + * Always accept broadcast frames. + */ + rxfilt |= RGE_RXCFG_INDIV | RGE_RXCFG_BROAD; + + if ((if_getflags(sc->sc_ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { + rxfilt |= RGE_RXCFG_MULTI; + if ((if_getflags(sc->sc_ifp) & IFF_PROMISC) != 0) + rxfilt |= RGE_RXCFG_ALLPHYS; + hashes[0] = hashes[1] = 0xffffffff; + } else { + rxfilt |= RGE_RXCFG_MULTI; + /* Program new filter. */ + memset(hashes, 0, sizeof(hashes)); + if_foreach_llmaddr(sc->sc_ifp, rge_hash_maddr, &hashes); + } + + RGE_WRITE_4(sc, RGE_RXCFG, rxfilt); + RGE_WRITE_4(sc, RGE_MAR0, bswap32(hashes[1])); + RGE_WRITE_4(sc, RGE_MAR4, bswap32(hashes[0])); +} + +static void +rge_add_media_types(struct rge_softc *sc) +{ + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_2500_T | IFM_FDX, 0, NULL); + + if (sc->rge_type == MAC_R26) { + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_5000_T | IFM_FDX, + 0, NULL); + } else if (sc->rge_type == MAC_R27) { + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T, 0, NULL); + ifmedia_add(&sc->sc_media, IFM_ETHER | IFM_10G_T | IFM_FDX, + 0, NULL); + } +} + +/** + * @brief Deferred packet dequeue and submit. + */ +static void +rge_tx_task(void *arg, int npending) +{ + struct rge_softc *sc = (struct rge_softc *) arg; + /* Note: for now, one queue */ + struct rge_queues *q = sc->sc_queues; + struct mbuf *m; + int ntx = 0; + int idx, free, used; + + RGE_DPRINTF(sc, RGE_DEBUG_XMIT, "%s: running\n", __func__); + + RGE_LOCK(sc); + sc->sc_drv_stats.tx_task_cnt++; + + if (sc->sc_stopped == true) { + sc->sc_watchdog = 0; + RGE_UNLOCK(sc); + return; + } + + /* Calculate free space. */ + idx = q->q_tx.rge_txq_prodidx; + free = q->q_tx.rge_txq_considx; + if (free <= idx) + free += RGE_TX_LIST_CNT; + free -= idx; + + for (;;) { + if (free < RGE_TX_NSEGS + 2) { + break; + } + + /* Dequeue */ + m = mbufq_dequeue(&sc->sc_txq); + if (m == NULL) + break; + + /* Attempt to encap */ + used = rge_encap(sc, q, m, idx); + if (used < 0) { + if_inc_counter(sc->sc_ifp, IFCOUNTER_OQDROPS, 1); + m_freem(m); + continue; + } else if (used == 0) { + mbufq_prepend(&sc->sc_txq, m); + break; + } + + /* + * Note: mbuf is now owned by the tx ring, but we hold the + * lock so it's safe to pass it up here to be copied without + * worrying the TX task will run and dequeue/free it before + * we get a shot at it. + */ + ETHER_BPF_MTAP(sc->sc_ifp, m); + + /* Update free/idx pointers */ + free -= used; + idx += used; + if (idx >= RGE_TX_LIST_CNT) + idx -= RGE_TX_LIST_CNT; + + ntx++; + } + + /* Ok, did we queue anything? If so, poke the hardware */ + if (ntx > 0) { + q->q_tx.rge_txq_prodidx = idx; + sc->sc_watchdog = 5; + RGE_WRITE_2(sc, RGE_TXSTART, RGE_TXSTART_START); + } + + RGE_DPRINTF(sc, RGE_DEBUG_XMIT, + "%s: handled %d frames; prod=%d, cons=%d\n", __func__, + ntx, q->q_tx.rge_txq_prodidx, q->q_tx.rge_txq_considx); + + RGE_UNLOCK(sc); +} + +/** + * @brief Called by the sc_timeout callout. + * + * This is called by the callout code with the driver lock held. + */ +void +rge_tick(void *arg) +{ + struct rge_softc *sc = arg; + + RGE_ASSERT_LOCKED(sc); + + rge_link_state(sc); + + /* + * Since we don't have any other place yet to trigger/test this, + * let's do it here every second and just bite the driver + * blocking for a little bit whilst it happens. + */ + if ((if_getdrvflags(sc->sc_ifp) & IFF_DRV_RUNNING) != 0) + rge_hw_mac_stats_fetch(sc, &sc->sc_mac_stats.lcl_stats); + + /* + * Handle the TX watchdog. + */ + if (sc->sc_watchdog > 0) { + sc->sc_watchdog--; + if (sc->sc_watchdog == 0) { + RGE_PRINT_ERROR(sc, "TX timeout (watchdog)\n"); + rge_init_locked(sc); + sc->sc_drv_stats.tx_watchdog_timeout_cnt++; + } + } + + callout_reset(&sc->sc_timeout, hz, rge_tick, sc); +} + +/** + * @brief process a link state change. + * + * Must be called with the driver lock held. + */ +void +rge_link_state(struct rge_softc *sc) +{ + int link = LINK_STATE_DOWN; + + RGE_ASSERT_LOCKED(sc); + + if (rge_get_link_status(sc)) + link = LINK_STATE_UP; + + if (if_getlinkstate(sc->sc_ifp) != link) { + sc->sc_drv_stats.link_state_change_cnt++; + if_link_state_change(sc->sc_ifp, link); + } +} + +/** + * @brief Suspend + */ +static int +rge_suspend(device_t dev) +{ + struct rge_softc *sc = device_get_softc(dev); + + RGE_LOCK(sc); + rge_stop_locked(sc); + /* TODO: wake on lan */ + sc->sc_suspended = true; + RGE_UNLOCK(sc); + + return (0); +} + +/** + * @brief Resume + */ +static int +rge_resume(device_t dev) +{ + struct rge_softc *sc = device_get_softc(dev); + + RGE_LOCK(sc); + /* TODO: wake on lan */ + + /* reinit if required */ + if (if_getflags(sc->sc_ifp) & IFF_UP) + rge_init_locked(sc); + + sc->sc_suspended = false; + + RGE_UNLOCK(sc); + + return (0); +} + +/** + * @brief Shutdown the driver during shutdown + */ +static int +rge_shutdown(device_t dev) +{ + struct rge_softc *sc = device_get_softc(dev); + + RGE_LOCK(sc); + rge_stop_locked(sc); + RGE_UNLOCK(sc); + + return (0); +} + +static device_method_t rge_methods[] = { + DEVMETHOD(device_probe, rge_probe), + DEVMETHOD(device_attach, rge_attach), + DEVMETHOD(device_detach, rge_detach), + + DEVMETHOD(device_suspend, rge_suspend), + DEVMETHOD(device_resume, rge_resume), + DEVMETHOD(device_shutdown, rge_shutdown), + + DEVMETHOD_END +}; + +static driver_t rge_driver = { + "rge", + rge_methods, + sizeof(struct rge_softc) +}; + +MODULE_DEPEND(rge, pci, 1, 1, 1); +MODULE_DEPEND(rge, ether, 1, 1, 1); + +DRIVER_MODULE_ORDERED(rge, pci, rge_driver, NULL, NULL, SI_ORDER_ANY); diff --git a/sys/dev/rge/if_rge_debug.h b/sys/dev/rge/if_rge_debug.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_debug.h @@ -0,0 +1,63 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __IF_RGE_DEBUG_H__ +#define __IF_RGE_DEBUG_H__ + +#define RGE_DEBUG_XMIT 0x00000001 +#define RGE_DEBUG_RECV 0x00000002 +#define RGE_DEBUG_INTR 0x00000004 +#define RGE_DEBUG_SETUP 0x00000008 +#define RGE_DEBUG_INIT 0x00000010 +#define RGE_DEBUG_XMIT_DESC 0x00000020 +#define RGE_DEBUG_RECV_DESC 0x00000040 + +#define RGE_DPRINTF(sc, dbg, ...) \ + do { \ + if (((sc)->sc_debug & (dbg)) != 0) \ + device_printf((sc)->sc_dev, __VA_ARGS__); \ + } while (0) + +#define RGE_DLOG(sc, dbg, ...) \ + do { \ + if (((sc)->sc_debug & (dbg)) != 0) \ + device_log((sc)->sc_dev, LOG_DEBUG, \ + __VA_ARGS__); \ + } while (0) + +#define RGE_PRINT_ERROR(sc, ...) \ + do { \ + device_printf((sc)->sc_dev, "[ERR] " __VA_ARGS__); \ + } while (0) + +#define RGE_PRINT_INFO(sc, ...) \ + do { \ + device_printf((sc)->sc_dev, "[INFO] " __VA_ARGS__); \ + } while (0) + +#define RGE_PRINT_TODO(sc, ...) \ + do { \ + device_printf((sc)->sc_dev, "[TODO] " __VA_ARGS__); \ + } while (0) + + +#define RGE_PRINT_WARN(sc, ...) \ + do { \ + device_printf((sc)->sc_dev, "[WARN] " __VA_ARGS__); \ + } while (0) + +#endif /* __IF_RGE_DEBUG_H__ */ diff --git a/sys/dev/rge/if_rge_hw.h b/sys/dev/rge/if_rge_hw.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_hw.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __IF_RGE_HW_H__ +#define __IF_RGE_HW_H__ + +struct rge_softc; + +extern int rge_chipinit(struct rge_softc *); +extern void rge_mac_config_mcu(struct rge_softc *, enum rge_mac_type); +extern void rge_write_mac_ocp(struct rge_softc *, uint16_t, uint16_t); +extern uint16_t rge_read_mac_ocp(struct rge_softc *, uint16_t); +extern void rge_ephy_config(struct rge_softc *); +extern int rge_phy_config(struct rge_softc *); +extern void rge_set_macaddr(struct rge_softc *, const uint8_t *); +extern void rge_get_macaddr(struct rge_softc *, uint8_t *); +extern void rge_hw_reset(struct rge_softc *); +extern void rge_config_imtype(struct rge_softc *, int); +extern void rge_disable_aspm_clkreq(struct rge_softc *); +extern void rge_setup_intr(struct rge_softc *, int); +extern void rge_write_csi(struct rge_softc *, uint32_t, uint32_t); +extern uint32_t rge_read_csi(struct rge_softc *, uint32_t); +extern void rge_write_phy(struct rge_softc *, uint16_t, uint16_t, uint16_t); +extern uint16_t rge_read_phy(struct rge_softc *, uint16_t, uint16_t); +extern void rge_write_phy_ocp(struct rge_softc *, uint16_t, uint16_t); +extern uint16_t rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg); +extern int rge_get_link_status(struct rge_softc *); + +#endif /* __IF_RGE_HW_H__ */ diff --git a/sys/dev/rge/if_rge_hw.c b/sys/dev/rge/if_rge_hw.c new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_hw.c @@ -0,0 +1,1935 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2023-2025 Kevin Lo + * Copyright (c) 2025 Adrian Chadd + * + * Hardware programming portions from Realtek Semiconductor. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rge.c,v 1.38 2025/09/19 00:41:14 kevlo Exp $ */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include "if_rge_vendor.h" +#include "if_rgereg.h" +#include "if_rgevar.h" +#include "if_rge_microcode.h" +#include "if_rge_debug.h" + +#include "if_rge_hw.h" + +static int rge_reset(struct rge_softc *sc); +static void rge_set_phy_power(struct rge_softc *sc, int on); +static uint64_t rge_mcu_get_bin_version(uint16_t entries); +static void rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever); +static void rge_ephy_config_mac_r25(struct rge_softc *sc); +static void rge_ephy_config_mac_r25b(struct rge_softc *sc); +static void rge_ephy_config_mac_r27(struct rge_softc *sc); +static void rge_phy_config_mac_r27(struct rge_softc *sc); +static void rge_phy_config_mac_r26(struct rge_softc *sc); +static void rge_phy_config_mac_r25(struct rge_softc *sc); +static void rge_phy_config_mac_r25b(struct rge_softc *sc); +static void rge_phy_config_mac_r25d(struct rge_softc *sc); +static void rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever); +static void rge_hw_init(struct rge_softc *sc); +static void rge_disable_phy_ocp_pwrsave(struct rge_softc *sc); +static void rge_patch_phy_mcu(struct rge_softc *sc, int set); +static void rge_disable_hw_im(struct rge_softc *sc); +static void rge_disable_sim_im(struct rge_softc *sc); +static void rge_setup_sim_im(struct rge_softc *sc); +static void rge_switch_mcu_ram_page(struct rge_softc *sc, int page); +static int rge_exit_oob(struct rge_softc *sc); +static void rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val); +static uint16_t rge_read_ephy(struct rge_softc *sc, uint16_t reg); +static uint16_t rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg); +static void rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val); + +static int +rge_reset(struct rge_softc *sc) +{ + int i; + + RGE_CLRBIT_4(sc, RGE_RXCFG, RGE_RXCFG_ALLPHYS | RGE_RXCFG_INDIV | + RGE_RXCFG_MULTI | RGE_RXCFG_BROAD | RGE_RXCFG_RUNT | + RGE_RXCFG_ERRPKT); + + /* Enable RXDV gate. */ + RGE_SETBIT_1(sc, RGE_PPSW, 0x08); + + RGE_SETBIT_1(sc, RGE_CMD, RGE_CMD_STOPREQ); + if (sc->rge_type == MAC_R25) { + for (i = 0; i < 20; i++) { + DELAY(10); + if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_STOPREQ)) + break; + } + if (i == 20) { + RGE_PRINT_ERROR(sc, "failed to stop all requests\n"); + return ETIMEDOUT; + } + } else + DELAY(200); + + for (i = 0; i < 3000; i++) { + DELAY(50); + if ((RGE_READ_1(sc, RGE_MCUCMD) & (RGE_MCUCMD_RXFIFO_EMPTY | + RGE_MCUCMD_TXFIFO_EMPTY)) == (RGE_MCUCMD_RXFIFO_EMPTY | + RGE_MCUCMD_TXFIFO_EMPTY)) + break; + } + if (sc->rge_type != MAC_R25) { + for (i = 0; i < 3000; i++) { + DELAY(50); + if ((RGE_READ_2(sc, RGE_IM) & 0x0103) == 0x0103) + break; + } + } + + RGE_WRITE_1(sc, RGE_CMD, + RGE_READ_1(sc, RGE_CMD) & (RGE_CMD_TXENB | RGE_CMD_RXENB)); + + /* Soft reset. */ + RGE_WRITE_1(sc, RGE_CMD, RGE_CMD_RESET); + + for (i = 0; i < RGE_TIMEOUT; i++) { + DELAY(100); + if (!(RGE_READ_1(sc, RGE_CMD) & RGE_CMD_RESET)) + break; + } + if (i == RGE_TIMEOUT) { + RGE_PRINT_ERROR(sc, "reset never completed!\n"); + return ETIMEDOUT; + } + + return 0; +} + +/** + * @brief Do initial chip power-on and setup. + * + * Must be called with the driver lock held. + */ +int +rge_chipinit(struct rge_softc *sc) +{ + int error; + + RGE_ASSERT_LOCKED(sc); + + if ((error = rge_exit_oob(sc)) != 0) + return error; + rge_set_phy_power(sc, 1); + rge_hw_init(sc); + rge_hw_reset(sc); + + return 0; +} + +static void +rge_set_phy_power(struct rge_softc *sc, int on) +{ + int i; + + if (on) { + RGE_SETBIT_1(sc, RGE_PMCH, 0xc0); + + rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN); + + for (i = 0; i < RGE_TIMEOUT; i++) { + if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 3) + break; + DELAY(1000); + } + } else { + rge_write_phy(sc, 0, MII_BMCR, BMCR_AUTOEN | BMCR_PDOWN); + RGE_CLRBIT_1(sc, RGE_PMCH, 0x80); + RGE_CLRBIT_1(sc, RGE_PPSW, 0x40); + } +} + +void +rge_mac_config_mcu(struct rge_softc *sc, enum rge_mac_type type) +{ + uint64_t mcodever; + uint16_t reg; + int i, npages; + + if (type == MAC_R25) { + for (npages = 0; npages < 3; npages++) { + rge_switch_mcu_ram_page(sc, npages); + for (i = 0; i < nitems(rtl8125_mac_bps); i++) { + if (npages == 0) + rge_write_mac_ocp(sc, + rtl8125_mac_bps[i].reg, + rtl8125_mac_bps[i].val); + else if (npages == 1) + rge_write_mac_ocp(sc, + rtl8125_mac_bps[i].reg, 0); + else { + if (rtl8125_mac_bps[i].reg < 0xf9f8) + rge_write_mac_ocp(sc, + rtl8125_mac_bps[i].reg, 0); + } + } + if (npages == 2) { + rge_write_mac_ocp(sc, 0xf9f8, 0x6486); + rge_write_mac_ocp(sc, 0xf9fa, 0x0b15); + rge_write_mac_ocp(sc, 0xf9fc, 0x090e); + rge_write_mac_ocp(sc, 0xf9fe, 0x1139); + } + } + rge_write_mac_ocp(sc, 0xfc26, 0x8000); + rge_write_mac_ocp(sc, 0xfc2a, 0x0540); + rge_write_mac_ocp(sc, 0xfc2e, 0x0a06); + rge_write_mac_ocp(sc, 0xfc30, 0x0eb8); + rge_write_mac_ocp(sc, 0xfc32, 0x3a5c); + rge_write_mac_ocp(sc, 0xfc34, 0x10a8); + rge_write_mac_ocp(sc, 0xfc40, 0x0d54); + rge_write_mac_ocp(sc, 0xfc42, 0x0e24); + rge_write_mac_ocp(sc, 0xfc48, 0x307a); + } else if (type == MAC_R25B) { + rge_switch_mcu_ram_page(sc, 0); + for (i = 0; i < nitems(rtl8125b_mac_bps); i++) { + rge_write_mac_ocp(sc, rtl8125b_mac_bps[i].reg, + rtl8125b_mac_bps[i].val); + } + } else if (type == MAC_R25D) { + for (npages = 0; npages < 3; npages++) { + rge_switch_mcu_ram_page(sc, npages); + + rge_write_mac_ocp(sc, 0xf800, + (npages == 0) ? 0xe002 : 0); + rge_write_mac_ocp(sc, 0xf802, + (npages == 0) ? 0xe006 : 0); + rge_write_mac_ocp(sc, 0xf804, + (npages == 0) ? 0x4166 : 0); + rge_write_mac_ocp(sc, 0xf806, + (npages == 0) ? 0x9cf6 : 0); + rge_write_mac_ocp(sc, 0xf808, + (npages == 0) ? 0xc002 : 0); + rge_write_mac_ocp(sc, 0xf80a, + (npages == 0) ? 0xb800 : 0); + rge_write_mac_ocp(sc, 0xf80c, + (npages == 0) ? 0x14a4 : 0); + rge_write_mac_ocp(sc, 0xf80e, + (npages == 0) ? 0xc102 : 0); + rge_write_mac_ocp(sc, 0xf810, + (npages == 0) ? 0xb900 : 0); + + for (reg = 0xf812; reg <= 0xf9f6; reg += 2) + rge_write_mac_ocp(sc, reg, 0); + + rge_write_mac_ocp(sc, 0xf9f8, + (npages == 2) ? 0x6938 : 0); + rge_write_mac_ocp(sc, 0xf9fa, + (npages == 2) ? 0x0a18 : 0); + rge_write_mac_ocp(sc, 0xf9fc, + (npages == 2) ? 0x0217 : 0); + rge_write_mac_ocp(sc, 0xf9fe, + (npages == 2) ? 0x0d2a : 0); + } + rge_write_mac_ocp(sc, 0xfc26, 0x8000); + rge_write_mac_ocp(sc, 0xfc28, 0x14a2); + rge_write_mac_ocp(sc, 0xfc48, 0x0001); + } else if (type == MAC_R27) { + mcodever = rge_mcu_get_bin_version(nitems(rtl8127_mac_bps)); + if (sc->rge_mcodever != mcodever) { + /* Switch to page 0. */ + rge_switch_mcu_ram_page(sc, 0); + for (i = 0; i < 256; i++) + rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg, + rtl8127_mac_bps[i].val); + /* Switch to page 1. */ + rge_switch_mcu_ram_page(sc, 1); + for (; i < nitems(rtl8127_mac_bps); i++) + rge_write_mac_ocp(sc, rtl8127_mac_bps[i].reg, + rtl8127_mac_bps[i].val); + } + rge_write_mac_ocp(sc, 0xfc26, 0x8000); + rge_write_mac_ocp(sc, 0xfc28, 0x1520); + rge_write_mac_ocp(sc, 0xfc2a, 0x41e0); + rge_write_mac_ocp(sc, 0xfc2c, 0x508c); + rge_write_mac_ocp(sc, 0xfc2e, 0x50f6); + rge_write_mac_ocp(sc, 0xfc30, 0x34fa); + rge_write_mac_ocp(sc, 0xfc32, 0x0166); + rge_write_mac_ocp(sc, 0xfc34, 0x1a6a); + rge_write_mac_ocp(sc, 0xfc36, 0x1a2c); + rge_write_mac_ocp(sc, 0xfc48, 0x00ff); + + /* Write microcode version. */ + rge_mcu_set_version(sc, mcodever); + } +} + +static uint64_t +rge_mcu_get_bin_version(uint16_t entries) +{ + uint64_t binver = 0; + int i; + + for (i = 0; i < 4; i++) { + binver <<= 16; + binver |= rtl8127_mac_bps[entries - 4 + i].val; + } + + return binver; +} + +static void +rge_mcu_set_version(struct rge_softc *sc, uint64_t mcodever) +{ + int i; + + /* Switch to page 2. */ + rge_switch_mcu_ram_page(sc, 2); + + for (i = 0; i < 8; i += 2) { + rge_write_mac_ocp(sc, 0xf9f8 + 6 - i, (uint16_t)mcodever); + mcodever >>= 16; + } + + /* Switch back to page 0. */ + rge_switch_mcu_ram_page(sc, 0); +} + +void +rge_ephy_config(struct rge_softc *sc) +{ + switch (sc->rge_type) { + case MAC_R25: + rge_ephy_config_mac_r25(sc); + break; + case MAC_R25B: + rge_ephy_config_mac_r25b(sc); + break; + case MAC_R27: + rge_ephy_config_mac_r27(sc); + break; + default: + break; /* Nothing to do. */ + } +} + +static void +rge_ephy_config_mac_r25(struct rge_softc *sc) +{ + uint16_t val; + int i; + + for (i = 0; i < nitems(mac_r25_ephy); i++) + rge_write_ephy(sc, mac_r25_ephy[i].reg, mac_r25_ephy[i].val); + + val = rge_read_ephy(sc, 0x002a) & ~0x7000; + rge_write_ephy(sc, 0x002a, val | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0019, 0x0040); + RGE_EPHY_SETBIT(sc, 0x001b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x001b, 0x7000); + rge_write_ephy(sc, 0x0002, 0x6042); + rge_write_ephy(sc, 0x0006, 0x0014); + val = rge_read_ephy(sc, 0x006a) & ~0x7000; + rge_write_ephy(sc, 0x006a, val | 0x3000); + RGE_EPHY_CLRBIT(sc, 0x0059, 0x0040); + RGE_EPHY_SETBIT(sc, 0x005b, 0x0e00); + RGE_EPHY_CLRBIT(sc, 0x005b, 0x7000); + rge_write_ephy(sc, 0x0042, 0x6042); + rge_write_ephy(sc, 0x0046, 0x0014); +} + +static void +rge_ephy_config_mac_r25b(struct rge_softc *sc) +{ + int i; + + for (i = 0; i < nitems(mac_r25b_ephy); i++) + rge_write_ephy(sc, mac_r25b_ephy[i].reg, mac_r25b_ephy[i].val); +} + +static void +rge_ephy_config_mac_r27(struct rge_softc *sc) +{ + int i; + + for (i = 0; i < nitems(mac_r27_ephy); i++) + rge_r27_write_ephy(sc, mac_r27_ephy[i].reg, + mac_r27_ephy[i].val); + + /* Clear extended address. */ + rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, 0); +} + +int +rge_phy_config(struct rge_softc *sc) +{ + uint16_t val = 0; + int i; + + rge_ephy_config(sc); + + /* PHY reset. */ + rge_write_phy(sc, 0, MII_ANAR, + rge_read_phy(sc, 0, MII_ANAR) & + ~(ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10)); + rge_write_phy(sc, 0, MII_100T2CR, + rge_read_phy(sc, 0, MII_100T2CR) & + ~(GTCR_ADV_1000TFDX | GTCR_ADV_1000THDX)); + switch (sc->rge_type) { + case MAC_R27: + val |= RGE_ADV_10000TFDX; + /* fallthrough */ + case MAC_R26: + val |= RGE_ADV_5000TFDX; + /* fallthrough */ + default: + val |= RGE_ADV_2500TFDX; + break; + } + RGE_PHY_CLRBIT(sc, 0xa5d4, val); + rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | + BMCR_STARTNEG); + for (i = 0; i < 2500; i++) { + if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET)) + break; + DELAY(1000); + } + if (i == 2500) { + RGE_PRINT_ERROR(sc, "PHY reset failed\n"); + return (ETIMEDOUT); + } + + /* Read ram code version. */ + rge_write_phy_ocp(sc, 0xa436, 0x801e); + sc->rge_rcodever = rge_read_phy_ocp(sc, 0xa438); + + switch (sc->rge_type) { + case MAC_R25: + rge_phy_config_mac_r25(sc); + break; + case MAC_R25B: + rge_phy_config_mac_r25b(sc); + break; + case MAC_R25D: + rge_phy_config_mac_r25d(sc); + break; + case MAC_R26: + rge_phy_config_mac_r26(sc); + break; + case MAC_R27: + rge_phy_config_mac_r27(sc); + break; + default: + break; /* Can't happen. */ + } + + RGE_PHY_CLRBIT(sc, 0xa5b4, 0x8000); + + /* Disable EEE. */ + RGE_MAC_CLRBIT(sc, 0xe040, 0x0003); + if (sc->rge_type == MAC_R25) { + RGE_MAC_CLRBIT(sc, 0xeb62, 0x0006); + RGE_PHY_CLRBIT(sc, 0xa432, 0x0010); + } else if (sc->rge_type == MAC_R25B || sc->rge_type == MAC_R25D) + RGE_PHY_SETBIT(sc, 0xa432, 0x0010); + + RGE_PHY_CLRBIT(sc, 0xa5d0, (sc->rge_type == MAC_R27) ? 0x000e : 0x0006); + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0001); + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) + RGE_PHY_CLRBIT(sc, 0xa6d4, 0x0002); + RGE_PHY_CLRBIT(sc, 0xa6d8, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa428, 0x0080); + RGE_PHY_CLRBIT(sc, 0xa4a2, 0x0200); + + /* Disable advanced EEE. */ + RGE_MAC_CLRBIT(sc, 0xe052, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa442, 0x3000); + RGE_PHY_CLRBIT(sc, 0xa430, 0x8000); + + return (0); +} + +static void +rge_phy_config_mac_r27(struct rge_softc *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg_value[] = + { 0x815a, 0x0150, 0x81f4, 0x0150, 0x828e, 0x0150, 0x81b1, 0x0000, + 0x824b, 0x0000, 0x82e5, 0x0000 }; + + static const uint16_t mac_cfg2_value[] = + { 0x88d7, 0x01a0, 0x88d9, 0x01a0, 0x8ffa, 0x002a, 0x8fee, 0xffdf, + 0x8ff0, 0xffff, 0x8ff2, 0x0a4a, 0x8ff4, 0xaa5a, 0x8ff6, 0x0a4a, + 0x8ff8, 0xaa5a }; + + static const uint16_t mac_cfg_a438_value[] = + { 0x003b, 0x0086, 0x00b7, 0x00db, 0x00fe, 0x00fe, 0x00fe, 0x00fe, + 0x00c3, 0x0078, 0x0047, 0x0023 }; + + rge_phy_config_mcu(sc, RGE_MAC_R27_RCODE_VER); + + rge_write_phy_ocp(sc, 0xa4d2, 0x0000); + rge_read_phy_ocp(sc, 0xa4d4); + + RGE_PHY_CLRBIT(sc, 0xa442, 0x0800); + rge_write_phy_ocp(sc, 0xa436, 0x8415); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x9300); + rge_write_phy_ocp(sc, 0xa436, 0x81a3); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); + rge_write_phy_ocp(sc, 0xa436, 0x81ae); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); + rge_write_phy_ocp(sc, 0xa436, 0x81b9); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xb900); + rge_write_phy_ocp(sc, 0xb87c, 0x83b0); + RGE_PHY_CLRBIT(sc,0xb87e, 0x0e00); + rge_write_phy_ocp(sc, 0xb87c, 0x83c5); + RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); + rge_write_phy_ocp(sc, 0xb87c, 0x83da); + RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); + rge_write_phy_ocp(sc, 0xb87c, 0x83ef); + RGE_PHY_CLRBIT(sc, 0xb87e, 0x0e00); + val = rge_read_phy_ocp(sc, 0xbf38) & ~0x01f0; + rge_write_phy_ocp(sc, 0xbf38, val | 0x0160); + val = rge_read_phy_ocp(sc, 0xbf3a) & ~0x001f; + rge_write_phy_ocp(sc, 0xbf3a, val | 0x0014); + RGE_PHY_CLRBIT(sc, 0xbf28, 0x6000); + RGE_PHY_CLRBIT(sc, 0xbf2c, 0xc000); + val = rge_read_phy_ocp(sc, 0xbf28) & ~0x1fff; + rge_write_phy_ocp(sc, 0xbf28, val | 0x0187); + val = rge_read_phy_ocp(sc, 0xbf2a) & ~0x003f; + rge_write_phy_ocp(sc, 0xbf2a, val | 0x0003); + rge_write_phy_ocp(sc, 0xa436, 0x8173); + rge_write_phy_ocp(sc, 0xa438, 0x8620); + rge_write_phy_ocp(sc, 0xa436, 0x8175); + rge_write_phy_ocp(sc, 0xa438, 0x8671); + rge_write_phy_ocp(sc, 0xa436, 0x817c); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x8187); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xA436, 0x8192); + RGE_PHY_SETBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xA436, 0x819D); + RGE_PHY_SETBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xA436, 0x81A8); + RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xA436, 0x81B3); + RGE_PHY_CLRBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xA436, 0x81BE); + RGE_PHY_SETBIT(sc, 0xA438, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x817d); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa600); + rge_write_phy_ocp(sc, 0xa436, 0x8188); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa600); + rge_write_phy_ocp(sc, 0xa436, 0x8193); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa600); + rge_write_phy_ocp(sc, 0xa436, 0x819e); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa600); + rge_write_phy_ocp(sc, 0xa436, 0x81a9); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1400); + rge_write_phy_ocp(sc, 0xa436, 0x81b4); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1400); + rge_write_phy_ocp(sc, 0xa436, 0x81bf); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xa600); + RGE_PHY_CLRBIT(sc, 0xaeaa, 0x0028); + rge_write_phy_ocp(sc, 0xb87c, 0x84f0); + rge_write_phy_ocp(sc, 0xb87e, 0x201c); + rge_write_phy_ocp(sc, 0xb87c, 0x84f2); + rge_write_phy_ocp(sc, 0xb87e, 0x3117); + rge_write_phy_ocp(sc, 0xaec6, 0x0000); + rge_write_phy_ocp(sc, 0xae20, 0xffff); + rge_write_phy_ocp(sc, 0xaece, 0xffff); + rge_write_phy_ocp(sc, 0xaed2, 0xffff); + rge_write_phy_ocp(sc, 0xaec8, 0x0000); + RGE_PHY_CLRBIT(sc, 0xaed0, 0x0001); + rge_write_phy_ocp(sc, 0xadb8, 0x0150); + rge_write_phy_ocp(sc, 0xb87c, 0x8197); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); + rge_write_phy_ocp(sc, 0xb87c, 0x8231); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); + rge_write_phy_ocp(sc, 0xb87c, 0x82cb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5000); + rge_write_phy_ocp(sc, 0xb87c, 0x82cd); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); + rge_write_phy_ocp(sc, 0xb87c, 0x8233); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); + rge_write_phy_ocp(sc, 0xb87c, 0x8199); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5700); + for (i = 0; i < nitems(mac_cfg_value); i+=2) { + rge_write_phy_ocp(sc, 0xb87c, mac_cfg_value[i]); + rge_write_phy_ocp(sc, 0xb87e, mac_cfg_value[i + 1]); + } + rge_write_phy_ocp(sc, 0xb87c, 0x84f7); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x2800); + RGE_PHY_SETBIT(sc, 0xaec2, 0x1000); + rge_write_phy_ocp(sc, 0xb87c, 0x81b3); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); + rge_write_phy_ocp(sc, 0xb87c, 0x824d); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); + rge_write_phy_ocp(sc, 0xb87c, 0x82e7); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xad00); + val = rge_read_phy_ocp(sc, 0xae4e) & ~0x000f; + rge_write_phy_ocp(sc, 0xae4e, val | 0x0001); + rge_write_phy_ocp(sc, 0xb87c, 0x82ce); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xf000; + rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); + rge_write_phy_ocp(sc, 0xb87c, 0x84ac); + rge_write_phy_ocp(sc, 0xb87e, 0x0000); + rge_write_phy_ocp(sc, 0xb87c, 0x84ae); + rge_write_phy_ocp(sc, 0xb87e, 0x0000); + rge_write_phy_ocp(sc, 0xb87c, 0x84b0); + rge_write_phy_ocp(sc, 0xb87e, 0xf818); + rge_write_phy_ocp(sc, 0xb87c, 0x84b2); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x6000); + rge_write_phy_ocp(sc, 0xb87c, 0x8ffc); + rge_write_phy_ocp(sc, 0xb87e, 0x6008); + rge_write_phy_ocp(sc, 0xb87c, 0x8ffe); + rge_write_phy_ocp(sc, 0xb87e, 0xf450); + rge_write_phy_ocp(sc, 0xb87c, 0x8015); + RGE_PHY_SETBIT(sc, 0xb87e, 0x0200); + rge_write_phy_ocp(sc, 0xb87c, 0x8016); + RGE_PHY_CLRBIT(sc, 0xb87e, 0x0800); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe6); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); + rge_write_phy_ocp(sc, 0xb87e, 0x2114); + rge_write_phy_ocp(sc, 0xb87c, 0x8647); + rge_write_phy_ocp(sc, 0xb87e, 0xa7B1); + rge_write_phy_ocp(sc, 0xb87c, 0x8649); + rge_write_phy_ocp(sc, 0xb87e, 0xbbca); + rge_write_phy_ocp(sc, 0xb87c, 0x864b); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xdc00); + rge_write_phy_ocp(sc, 0xb87c, 0x8154); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xc000; + rge_write_phy_ocp(sc, 0xb87e, val | 0x4000); + rge_write_phy_ocp(sc, 0xb87c, 0x8158); + RGE_PHY_CLRBIT(sc, 0xb87e, 0xc000); + rge_write_phy_ocp(sc, 0xb87c, 0x826c); + rge_write_phy_ocp(sc, 0xb87e, 0xffff); + rge_write_phy_ocp(sc, 0xb87c, 0x826e); + rge_write_phy_ocp(sc, 0xb87e, 0xffff); + rge_write_phy_ocp(sc, 0xb87c, 0x8872); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0e00); + rge_write_phy_ocp(sc, 0xa436, 0x8012); + RGE_PHY_SETBIT(sc, 0xa438, 0x0800); + rge_write_phy_ocp(sc, 0xa436, 0x8012); + RGE_PHY_SETBIT(sc, 0xa438, 0x4000); + RGE_PHY_SETBIT(sc, 0xb576, 0x0001); + rge_write_phy_ocp(sc, 0xa436, 0x834a); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x8217); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0x3f00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x2a00); + rge_write_phy_ocp(sc, 0xa436, 0x81b1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0b00); + rge_write_phy_ocp(sc, 0xb87c, 0x8fed); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x4e00); + rge_write_phy_ocp(sc, 0xb87c, 0x88ac); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x2300); + RGE_PHY_SETBIT(sc, 0xbf0c, 0x3800); + rge_write_phy_ocp(sc, 0xb87c, 0x88de); + RGE_PHY_CLRBIT(sc, 0xb87e, 0xFF00); + rge_write_phy_ocp(sc, 0xb87c, 0x80B4); + rge_write_phy_ocp(sc, 0xb87e, 0x5195); + rge_write_phy_ocp(sc, 0xa436, 0x8370); + rge_write_phy_ocp(sc, 0xa438, 0x8671); + rge_write_phy_ocp(sc, 0xa436, 0x8372); + rge_write_phy_ocp(sc, 0xa438, 0x86c8); + rge_write_phy_ocp(sc, 0xa436, 0x8401); + rge_write_phy_ocp(sc, 0xa438, 0x86c8); + rge_write_phy_ocp(sc, 0xa436, 0x8403); + rge_write_phy_ocp(sc, 0xa438, 0x86da); + rge_write_phy_ocp(sc, 0xa436, 0x8406); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x8408); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x840a); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x840c); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x840e); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x8410); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x8412); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x8414); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x8416); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x1800; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x82bd); + rge_write_phy_ocp(sc, 0xa438, 0x1f40); + val = rge_read_phy_ocp(sc, 0xbfb4) & ~0x07ff; + rge_write_phy_ocp(sc, 0xbfb4, val | 0x0328); + rge_write_phy_ocp(sc, 0xbfb6, 0x3e14); + rge_write_phy_ocp(sc, 0xa436, 0x81c4); + for (i = 0; i < nitems(mac_cfg_a438_value); i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg_a438_value[i]); + for (i = 0; i < nitems(mac_cfg2_value); i+=2) { + rge_write_phy_ocp(sc, 0xb87c, mac_cfg2_value[i]); + rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_value[i + 1]); + } + rge_write_phy_ocp(sc, 0xb87c, 0x88d5); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); + rge_write_phy_ocp(sc, 0xa436, 0x84bb); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); + rge_write_phy_ocp(sc, 0xa436, 0x84c0); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1600); + RGE_PHY_SETBIT(sc, 0xa430, 0x0003); +} + +static void +rge_phy_config_mac_r26(struct rge_softc *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg2_a438_value[] = + { 0x0044, 0x00a8, 0x00d6, 0x00ec, 0x00f6, 0x00fc, 0x00fe, + 0x00fe, 0x00bc, 0x0058, 0x002a, 0x003f, 0x3f02, 0x023c, + 0x3b0a, 0x1c00, 0x0000, 0x0000, 0x0000, 0x0000 }; + + static const uint16_t mac_cfg2_b87e_value[] = + { 0x03ed, 0x03ff, 0x0009, 0x03fe, 0x000b, 0x0021, 0x03f7, + 0x03b8, 0x03e0, 0x0049, 0x0049, 0x03e0, 0x03b8, 0x03f7, + 0x0021, 0x000b, 0x03fe, 0x0009, 0x03ff, 0x03ed, 0x000e, + 0x03fe, 0x03ed, 0x0006, 0x001a, 0x03f1, 0x03d8, 0x0023, + 0x0054, 0x0322, 0x00dd, 0x03ab, 0x03dc, 0x0027, 0x000e, + 0x03e5, 0x03f9, 0x0012, 0x0001, 0x03f1 }; + + rge_phy_config_mcu(sc, RGE_MAC_R26_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + rge_write_phy_ocp(sc, 0xa436, 0x80bf); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xed00); + rge_write_phy_ocp(sc, 0xa436, 0x80cd); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1000); + rge_write_phy_ocp(sc, 0xa436, 0x80d1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xc800); + rge_write_phy_ocp(sc, 0xa436, 0x80d4); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xc800); + rge_write_phy_ocp(sc, 0xa436, 0x80e1); + rge_write_phy_ocp(sc, 0xa438, 0x10cc); + rge_write_phy_ocp(sc, 0xa436, 0x80e5); + rge_write_phy_ocp(sc, 0xa438, 0x4f0c); + rge_write_phy_ocp(sc, 0xa436, 0x8387); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x4700); + val = rge_read_phy_ocp(sc, 0xa80c) & ~0x00c0; + rge_write_phy_ocp(sc, 0xa80c, val | 0x0080); + RGE_PHY_CLRBIT(sc, 0xac90, 0x0010); + RGE_PHY_CLRBIT(sc, 0xad2c, 0x8000); + rge_write_phy_ocp(sc, 0xb87c, 0x8321); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); + RGE_PHY_SETBIT(sc, 0xacf8, 0x000c); + rge_write_phy_ocp(sc, 0xa436, 0x8183); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5900); + RGE_PHY_SETBIT(sc, 0xad94, 0x0020); + RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); + RGE_PHY_SETBIT(sc, 0xb648, 0x4000); + rge_write_phy_ocp(sc, 0xb87c, 0x839e); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x2f00); + rge_write_phy_ocp(sc, 0xb87c, 0x83f2); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + RGE_PHY_SETBIT(sc, 0xada0, 0x0002); + rge_write_phy_ocp(sc, 0xb87c, 0x80f3); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x9900); + rge_write_phy_ocp(sc, 0xb87c, 0x8126); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xc100); + rge_write_phy_ocp(sc, 0xb87c, 0x893a); + rge_write_phy_ocp(sc, 0xb87e, 0x8080); + rge_write_phy_ocp(sc, 0xb87c, 0x8647); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); + rge_write_phy_ocp(sc, 0xb87c, 0x862c); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x1200); + rge_write_phy_ocp(sc, 0xb87c, 0x864a); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0xe600); + rge_write_phy_ocp(sc, 0xb87c, 0x80a0); + rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); + rge_write_phy_ocp(sc, 0xb87c, 0x805e); + rge_write_phy_ocp(sc, 0xb87e, 0xbcbc); + rge_write_phy_ocp(sc, 0xb87c, 0x8056); + rge_write_phy_ocp(sc, 0xb87e, 0x3077); + rge_write_phy_ocp(sc, 0xb87c, 0x8058); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8098); + rge_write_phy_ocp(sc, 0xb87e, 0x3077); + rge_write_phy_ocp(sc, 0xb87c, 0x809a); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x5a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8052); + rge_write_phy_ocp(sc, 0xb87e, 0x3733); + rge_write_phy_ocp(sc, 0xb87c, 0x8094); + rge_write_phy_ocp(sc, 0xb87e, 0x3733); + rge_write_phy_ocp(sc, 0xb87c, 0x807f); + rge_write_phy_ocp(sc, 0xb87e, 0x7c75); + rge_write_phy_ocp(sc, 0xb87c, 0x803d); + rge_write_phy_ocp(sc, 0xb87e, 0x7c75); + rge_write_phy_ocp(sc, 0xb87c, 0x8036); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); + rge_write_phy_ocp(sc, 0xb87c, 0x8078); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3000); + rge_write_phy_ocp(sc, 0xb87c, 0x8031); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); + rge_write_phy_ocp(sc, 0xb87c, 0x8073); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3300); + val = rge_read_phy_ocp(sc, 0xae06) & ~0xfc00; + rge_write_phy_ocp(sc, 0xae06, val | 0x7c00); + rge_write_phy_ocp(sc, 0xb87c, 0x89D1); + rge_write_phy_ocp(sc, 0xb87e, 0x0004); + rge_write_phy_ocp(sc, 0xa436, 0x8fbd); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0a00); + rge_write_phy_ocp(sc, 0xa436, 0x8fbe); + rge_write_phy_ocp(sc, 0xa438, 0x0d09); + rge_write_phy_ocp(sc, 0xb87c, 0x89cd); + rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); + rge_write_phy_ocp(sc, 0xb87c, 0x89cf); + rge_write_phy_ocp(sc, 0xb87e, 0x0f0f); + rge_write_phy_ocp(sc, 0xb87c, 0x83a4); + rge_write_phy_ocp(sc, 0xb87e, 0x6600); + rge_write_phy_ocp(sc, 0xb87c, 0x83a6); + rge_write_phy_ocp(sc, 0xb87e, 0x6601); + rge_write_phy_ocp(sc, 0xb87c, 0x83c0); + rge_write_phy_ocp(sc, 0xb87e, 0x6600); + rge_write_phy_ocp(sc, 0xb87c, 0x83c2); + rge_write_phy_ocp(sc, 0xb87e, 0x6601); + rge_write_phy_ocp(sc, 0xb87c, 0x8414); + rge_write_phy_ocp(sc, 0xb87e, 0x6600); + rge_write_phy_ocp(sc, 0xb87c, 0x8416); + rge_write_phy_ocp(sc, 0xb87e, 0x6601); + rge_write_phy_ocp(sc, 0xb87c, 0x83f8); + rge_write_phy_ocp(sc, 0xb87e, 0x6600); + rge_write_phy_ocp(sc, 0xb87c, 0x83fa); + rge_write_phy_ocp(sc, 0xb87e, 0x6601); + + rge_patch_phy_mcu(sc, 1); + val = rge_read_phy_ocp(sc, 0xbd96) & ~0x1f00; + rge_write_phy_ocp(sc, 0xbd96, val | 0x1000); + val = rge_read_phy_ocp(sc, 0xbf1c) & ~0x0007; + rge_write_phy_ocp(sc, 0xbf1c, val | 0x0007); + RGE_PHY_CLRBIT(sc, 0xbfbe, 0x8000); + val = rge_read_phy_ocp(sc, 0xbf40) & ~0x0380; + rge_write_phy_ocp(sc, 0xbf40, val | 0x0280); + val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0080; + rge_write_phy_ocp(sc, 0xbf90, val | 0x0060); + val = rge_read_phy_ocp(sc, 0xbf90) & ~0x0010; + rge_write_phy_ocp(sc, 0xbf90, val | 0x000c); + rge_patch_phy_mcu(sc, 0); + + rge_write_phy_ocp(sc, 0xa436, 0x843b); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x843d); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x2000); + RGE_PHY_CLRBIT(sc, 0xb516, 0x007f); + RGE_PHY_CLRBIT(sc, 0xbf80, 0x0030); + + rge_write_phy_ocp(sc, 0xa436, 0x8188); + for (i = 0; i < 11; i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); + + rge_write_phy_ocp(sc, 0xb87c, 0x8015); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + rge_write_phy_ocp(sc, 0xb87c, 0x8ffd); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0); + rge_write_phy_ocp(sc, 0xb87c, 0x8fff); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7f00); + rge_write_phy_ocp(sc, 0xb87c, 0x8ffb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); + rge_write_phy_ocp(sc, 0xb87e, 0x0002); + rge_write_phy_ocp(sc, 0xb87c, 0x8fef); + rge_write_phy_ocp(sc, 0xb87e, 0x00a5); + rge_write_phy_ocp(sc, 0xb87c, 0x8ff1); + rge_write_phy_ocp(sc, 0xb87e, 0x0106); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe1); + rge_write_phy_ocp(sc, 0xb87e, 0x0102); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe3); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0400); + RGE_PHY_SETBIT(sc, 0xa654, 0x0800); + RGE_PHY_CLRBIT(sc, 0xa654, 0x0003); + rge_write_phy_ocp(sc, 0xac3a, 0x5851); + val = rge_read_phy_ocp(sc, 0xac3c) & ~0xd000; + rge_write_phy_ocp(sc, 0xac3c, val | 0x2000); + val = rge_read_phy_ocp(sc, 0xac42) & ~0x0200; + rge_write_phy_ocp(sc, 0xac42, val | 0x01c0); + RGE_PHY_CLRBIT(sc, 0xac3e, 0xe000); + RGE_PHY_CLRBIT(sc, 0xac42, 0x0038); + val = rge_read_phy_ocp(sc, 0xac42) & ~0x0002; + rge_write_phy_ocp(sc, 0xac42, val | 0x0005); + rge_write_phy_ocp(sc, 0xac1a, 0x00db); + rge_write_phy_ocp(sc, 0xade4, 0x01b5); + RGE_PHY_CLRBIT(sc, 0xad9c, 0x0c00); + rge_write_phy_ocp(sc, 0xb87c, 0x814b); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); + rge_write_phy_ocp(sc, 0xb87c, 0x814d); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x1100); + rge_write_phy_ocp(sc, 0xb87c, 0x814f); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0b00); + rge_write_phy_ocp(sc, 0xb87c, 0x8142); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8144); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8150); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8118); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x811a); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x811c); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + rge_write_phy_ocp(sc, 0xb87c, 0x810f); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8111); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x811d); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + RGE_PHY_SETBIT(sc, 0xac36, 0x1000); + RGE_PHY_CLRBIT(sc, 0xad1c, 0x0100); + val = rge_read_phy_ocp(sc, 0xade8) & ~0xffc0; + rge_write_phy_ocp(sc, 0xade8, val | 0x1400); + rge_write_phy_ocp(sc, 0xb87c, 0x864b); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x9d00); + + rge_write_phy_ocp(sc, 0xa436, 0x8f97); + for (; i < nitems(mac_cfg2_a438_value); i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg2_a438_value[i]); + + RGE_PHY_SETBIT(sc, 0xad9c, 0x0020); + rge_write_phy_ocp(sc, 0xb87c, 0x8122); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); + + rge_write_phy_ocp(sc, 0xb87c, 0x82c8); + for (i = 0; i < 20; i++) + rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); + + rge_write_phy_ocp(sc, 0xb87c, 0x80ef); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0c00); + + rge_write_phy_ocp(sc, 0xb87c, 0x82a0); + for (; i < nitems(mac_cfg2_b87e_value); i++) + rge_write_phy_ocp(sc, 0xb87e, mac_cfg2_b87e_value[i]); + + rge_write_phy_ocp(sc, 0xa436, 0x8018); + RGE_PHY_SETBIT(sc, 0xa438, 0x2000); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe4); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0); + val = rge_read_phy_ocp(sc, 0xb54c) & ~0xffc0; + rge_write_phy_ocp(sc, 0xb54c, val | 0x3700); +} + +static void +rge_phy_config_mac_r25(struct rge_softc *sc) +{ + uint16_t val; + int i; + static const uint16_t mac_cfg3_a438_value[] = + { 0x0043, 0x00a7, 0x00d6, 0x00ec, 0x00f6, 0x00fb, 0x00fd, 0x00ff, + 0x00bb, 0x0058, 0x0029, 0x0013, 0x0009, 0x0004, 0x0002 }; + + static const uint16_t mac_cfg3_b88e_value[] = + { 0xc091, 0x6e12, 0xc092, 0x1214, 0xc094, 0x1516, 0xc096, 0x171b, + 0xc098, 0x1b1c, 0xc09a, 0x1f1f, 0xc09c, 0x2021, 0xc09e, 0x2224, + 0xc0a0, 0x2424, 0xc0a2, 0x2424, 0xc0a4, 0x2424, 0xc018, 0x0af2, + 0xc01a, 0x0d4a, 0xc01c, 0x0f26, 0xc01e, 0x118d, 0xc020, 0x14f3, + 0xc022, 0x175a, 0xc024, 0x19c0, 0xc026, 0x1c26, 0xc089, 0x6050, + 0xc08a, 0x5f6e, 0xc08c, 0x6e6e, 0xc08e, 0x6e6e, 0xc090, 0x6e12 }; + + rge_phy_config_mcu(sc, RGE_MAC_R25_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xad4e, 0x0010); + val = rge_read_phy_ocp(sc, 0xad16) & ~0x03ff; + rge_write_phy_ocp(sc, 0xad16, val | 0x03ff); + val = rge_read_phy_ocp(sc, 0xad32) & ~0x003f; + rge_write_phy_ocp(sc, 0xad32, val | 0x0006); + RGE_PHY_CLRBIT(sc, 0xac08, 0x1000); + RGE_PHY_CLRBIT(sc, 0xac08, 0x0100); + val = rge_read_phy_ocp(sc, 0xacc0) & ~0x0003; + rge_write_phy_ocp(sc, 0xacc0, val | 0x0002); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x00e0; + rge_write_phy_ocp(sc, 0xad40, val | 0x0040); + val = rge_read_phy_ocp(sc, 0xad40) & ~0x0007; + rge_write_phy_ocp(sc, 0xad40, val | 0x0004); + RGE_PHY_CLRBIT(sc, 0xac14, 0x0080); + RGE_PHY_CLRBIT(sc, 0xac80, 0x0300); + val = rge_read_phy_ocp(sc, 0xac5e) & ~0x0007; + rge_write_phy_ocp(sc, 0xac5e, val | 0x0002); + rge_write_phy_ocp(sc, 0xad4c, 0x00a8); + rge_write_phy_ocp(sc, 0xac5c, 0x01ff); + val = rge_read_phy_ocp(sc, 0xac8a) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac8a, val | 0x0030); + rge_write_phy_ocp(sc, 0xb87c, 0x8157); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + rge_write_phy_ocp(sc, 0xb87c, 0x8159); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0700); + rge_write_phy_ocp(sc, 0xb87c, 0x80a2); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + rge_write_phy_ocp(sc, 0xb87c, 0x809c); + rge_write_phy_ocp(sc, 0xb87e, 0x0153); + + rge_write_phy_ocp(sc, 0xa436, 0x81b3); + for (i = 0; i < nitems(mac_cfg3_a438_value); i++) + rge_write_phy_ocp(sc, 0xa438, mac_cfg3_a438_value[i]); + for (i = 0; i < 26; i++) + rge_write_phy_ocp(sc, 0xa438, 0); + rge_write_phy_ocp(sc, 0xa436, 0x8257); + rge_write_phy_ocp(sc, 0xa438, 0x020f); + rge_write_phy_ocp(sc, 0xa436, 0x80ea); + rge_write_phy_ocp(sc, 0xa438, 0x7843); + + rge_patch_phy_mcu(sc, 1); + RGE_PHY_CLRBIT(sc, 0xb896, 0x0001); + RGE_PHY_CLRBIT(sc, 0xb892, 0xff00); + for (i = 0; i < nitems(mac_cfg3_b88e_value); i += 2) { + rge_write_phy_ocp(sc, 0xb88e, mac_cfg3_b88e_value[i]); + rge_write_phy_ocp(sc, 0xb890, mac_cfg3_b88e_value[i + 1]); + } + RGE_PHY_SETBIT(sc, 0xb896, 0x0001); + rge_patch_phy_mcu(sc, 0); + + RGE_PHY_SETBIT(sc, 0xd068, 0x2000); + rge_write_phy_ocp(sc, 0xa436, 0x81a2); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + val = rge_read_phy_ocp(sc, 0xb54c) & ~0xff00; + rge_write_phy_ocp(sc, 0xb54c, val | 0xdb00); + RGE_PHY_CLRBIT(sc, 0xa454, 0x0001); + RGE_PHY_SETBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xad4e, 0x0010); + RGE_PHY_CLRBIT(sc, 0xa86a, 0x0001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + RGE_PHY_SETBIT(sc, 0xa424, 0x0008); +} + +static void +rge_phy_config_mac_r25b(struct rge_softc *sc) +{ + uint16_t val; + int i; + + rge_phy_config_mcu(sc, RGE_MAC_R25B_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + val = rge_read_phy_ocp(sc, 0xac46) & ~0x00f0; + rge_write_phy_ocp(sc, 0xac46, val | 0x0090); + val = rge_read_phy_ocp(sc, 0xad30) & ~0x0003; + rge_write_phy_ocp(sc, 0xad30, val | 0x0001); + rge_write_phy_ocp(sc, 0xb87c, 0x80f5); + rge_write_phy_ocp(sc, 0xb87e, 0x760e); + rge_write_phy_ocp(sc, 0xb87c, 0x8107); + rge_write_phy_ocp(sc, 0xb87e, 0x360e); + rge_write_phy_ocp(sc, 0xb87c, 0x8551); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0800); + val = rge_read_phy_ocp(sc, 0xbf00) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf00, val | 0xa000); + val = rge_read_phy_ocp(sc, 0xbf46) & ~0x0f00; + rge_write_phy_ocp(sc, 0xbf46, val | 0x0300); + for (i = 0; i < 10; i++) { + rge_write_phy_ocp(sc, 0xa436, 0x8044 + i * 6); + rge_write_phy_ocp(sc, 0xa438, 0x2417); + } + RGE_PHY_SETBIT(sc, 0xa4ca, 0x0040); + val = rge_read_phy_ocp(sc, 0xbf84) & ~0xe000; + rge_write_phy_ocp(sc, 0xbf84, val | 0xa000); + rge_write_phy_ocp(sc, 0xa436, 0x8170); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x2700; + rge_write_phy_ocp(sc, 0xa438, val | 0xd800); + RGE_PHY_SETBIT(sc, 0xa424, 0x0008); +} + +static void +rge_phy_config_mac_r25d(struct rge_softc *sc) +{ + uint16_t val; + int i; + + rge_phy_config_mcu(sc, RGE_MAC_R25D_RCODE_VER); + + RGE_PHY_SETBIT(sc, 0xa442, 0x0800); + + rge_patch_phy_mcu(sc, 1); + RGE_PHY_SETBIT(sc, 0xbf96, 0x8000); + val = rge_read_phy_ocp(sc, 0xbf94) & ~0x0007; + rge_write_phy_ocp(sc, 0xbf94, val | 0x0005); + val = rge_read_phy_ocp(sc, 0xbf8e) & ~0x3c00; + rge_write_phy_ocp(sc, 0xbf8e, val | 0x2800); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + RGE_PHY_SETBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x4000); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0004); + RGE_PHY_SETBIT(sc, 0xbc82, 0xe000); + RGE_PHY_SETBIT(sc, 0xbc82, 0x1c00); + val = rge_read_phy_ocp(sc, 0xbc80) & ~0x001f; + rge_write_phy_ocp(sc, 0xbc80, val | 0x0005); + val = rge_read_phy_ocp(sc, 0xbc82) & ~0x00e0; + rge_write_phy_ocp(sc, 0xbc82, val | 0x0040); + RGE_PHY_SETBIT(sc, 0xbc82, 0x001c); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + val = rge_read_phy_ocp(sc, 0xbcd8) & ~0xc000; + rge_write_phy_ocp(sc, 0xbcd8, val | 0x8000); + RGE_PHY_CLRBIT(sc, 0xbcd8, 0xc000); + RGE_PHY_CLRBIT(sc, 0xbd70, 0x0100); + RGE_PHY_SETBIT(sc, 0xa466, 0x0002); + rge_write_phy_ocp(sc, 0xa436, 0x836a); + RGE_PHY_CLRBIT(sc, 0xa438, 0xff00); + rge_patch_phy_mcu(sc, 0); + + rge_write_phy_ocp(sc, 0xb87c, 0x832c); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0500); + val = rge_read_phy_ocp(sc, 0xb106) & ~0x0700; + rge_write_phy_ocp(sc, 0xb106, val | 0x0100); + val = rge_read_phy_ocp(sc, 0xb206) & ~0x0700; + rge_write_phy_ocp(sc, 0xb206, val | 0x0200); + val = rge_read_phy_ocp(sc, 0xb306) & ~0x0700; + rge_write_phy_ocp(sc, 0xb306, val | 0x0300); + rge_write_phy_ocp(sc, 0xb87c, 0x80cb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0300); + rge_write_phy_ocp(sc, 0xbcf4, 0x0000); + rge_write_phy_ocp(sc, 0xbcf6, 0x0000); + rge_write_phy_ocp(sc, 0xbc12, 0x0000); + rge_write_phy_ocp(sc, 0xb87c, 0x844d); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0200); + + rge_write_phy_ocp(sc, 0xb87c, 0x8feb); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0100); + rge_write_phy_ocp(sc, 0xb87c, 0x8fe9); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x0600); + + val = rge_read_phy_ocp(sc, 0xac7e) & ~0x01fc; + rge_write_phy_ocp(sc, 0xac7e, val | 0x00B4); + rge_write_phy_ocp(sc, 0xb87c, 0x8105); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8117); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3a00); + rge_write_phy_ocp(sc, 0xb87c, 0x8103); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x7400); + rge_write_phy_ocp(sc, 0xb87c, 0x8115); + val = rge_read_phy_ocp(sc, 0xb87e) & ~0xff00; + rge_write_phy_ocp(sc, 0xb87e, val | 0x3400); + RGE_PHY_CLRBIT(sc, 0xad40, 0x0030); + val = rge_read_phy_ocp(sc, 0xad66) & ~0x000f; + rge_write_phy_ocp(sc, 0xad66, val | 0x0007); + val = rge_read_phy_ocp(sc, 0xad68) & ~0xf000; + rge_write_phy_ocp(sc, 0xad68, val | 0x8000); + val = rge_read_phy_ocp(sc, 0xad68) & ~0x0f00; + rge_write_phy_ocp(sc, 0xad68, val | 0x0500); + val = rge_read_phy_ocp(sc, 0xad68) & ~0x000f; + rge_write_phy_ocp(sc, 0xad68, val | 0x0002); + val = rge_read_phy_ocp(sc, 0xad6a) & ~0xf000; + rge_write_phy_ocp(sc, 0xad6a, val | 0x7000); + rge_write_phy_ocp(sc, 0xac50, 0x01e8); + rge_write_phy_ocp(sc, 0xa436, 0x81fa); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5400); + val = rge_read_phy_ocp(sc, 0xa864) & ~0x00f0; + rge_write_phy_ocp(sc, 0xa864, val | 0x00c0); + val = rge_read_phy_ocp(sc, 0xa42c) & ~0x00ff; + rge_write_phy_ocp(sc, 0xa42c, val | 0x0002); + rge_write_phy_ocp(sc, 0xa436, 0x80e1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0f00); + rge_write_phy_ocp(sc, 0xa436, 0x80de); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xf000; + rge_write_phy_ocp(sc, 0xa438, val | 0x0700); + RGE_PHY_SETBIT(sc, 0xa846, 0x0080); + rge_write_phy_ocp(sc, 0xa436, 0x80ba); + rge_write_phy_ocp(sc, 0xa438, 0x8a04); + rge_write_phy_ocp(sc, 0xa436, 0x80bd); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xca00); + rge_write_phy_ocp(sc, 0xa436, 0x80b7); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xb300); + rge_write_phy_ocp(sc, 0xa436, 0x80ce); + rge_write_phy_ocp(sc, 0xa438, 0x8a04); + rge_write_phy_ocp(sc, 0xa436, 0x80d1); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xca00); + rge_write_phy_ocp(sc, 0xa436, 0x80cb); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0xbb00); + rge_write_phy_ocp(sc, 0xa436, 0x80a6); + rge_write_phy_ocp(sc, 0xa438, 0x4909); + rge_write_phy_ocp(sc, 0xa436, 0x80a8); + rge_write_phy_ocp(sc, 0xa438, 0x05b8); + rge_write_phy_ocp(sc, 0xa436, 0x8200); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x5800); + rge_write_phy_ocp(sc, 0xa436, 0x8ff1); + rge_write_phy_ocp(sc, 0xa438, 0x7078); + rge_write_phy_ocp(sc, 0xa436, 0x8ff3); + rge_write_phy_ocp(sc, 0xa438, 0x5d78); + rge_write_phy_ocp(sc, 0xa436, 0x8ff5); + rge_write_phy_ocp(sc, 0xa438, 0x7862); + rge_write_phy_ocp(sc, 0xa436, 0x8ff7); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1400); + + rge_write_phy_ocp(sc, 0xa436, 0x814c); + rge_write_phy_ocp(sc, 0xa438, 0x8455); + rge_write_phy_ocp(sc, 0xa436, 0x814e); + rge_write_phy_ocp(sc, 0xa438, 0x84a6); + rge_write_phy_ocp(sc, 0xa436, 0x8163); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0600); + rge_write_phy_ocp(sc, 0xa436, 0x816a); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x0500); + rge_write_phy_ocp(sc, 0xa436, 0x8171); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1f00); + + val = rge_read_phy_ocp(sc, 0xbc3a) & ~0x000f; + rge_write_phy_ocp(sc, 0xbc3a, val | 0x0006); + for (i = 0; i < 10; i++) { + rge_write_phy_ocp(sc, 0xa436, 0x8064 + i * 3); + RGE_PHY_CLRBIT(sc, 0xa438, 0x0700); + } + val = rge_read_phy_ocp(sc, 0xbfa0) & ~0xff70; + rge_write_phy_ocp(sc, 0xbfa0, val | 0x5500); + rge_write_phy_ocp(sc, 0xbfa2, 0x9d00); + rge_write_phy_ocp(sc, 0xa436, 0x8165); + val = rge_read_phy_ocp(sc, 0xa438) & ~0x0700; + rge_write_phy_ocp(sc, 0xa438, val | 0x0200); + + rge_write_phy_ocp(sc, 0xa436, 0x8019); + RGE_PHY_SETBIT(sc, 0xa438, 0x0100); + rge_write_phy_ocp(sc, 0xa436, 0x8fe3); + rge_write_phy_ocp(sc, 0xa438, 0x0005); + rge_write_phy_ocp(sc, 0xa438, 0x0000); + rge_write_phy_ocp(sc, 0xa438, 0x00ed); + rge_write_phy_ocp(sc, 0xa438, 0x0502); + rge_write_phy_ocp(sc, 0xa438, 0x0b00); + rge_write_phy_ocp(sc, 0xa438, 0xd401); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x2900); + + rge_write_phy_ocp(sc, 0xa436, 0x8018); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1700); + + rge_write_phy_ocp(sc, 0xa436, 0x815b); + val = rge_read_phy_ocp(sc, 0xa438) & ~0xff00; + rge_write_phy_ocp(sc, 0xa438, val | 0x1700); + + RGE_PHY_CLRBIT(sc, 0xa4e0, 0x8000); + RGE_PHY_CLRBIT(sc, 0xa5d4, 0x0020); + RGE_PHY_CLRBIT(sc, 0xa654, 0x0800); + RGE_PHY_SETBIT(sc, 0xa430, 0x1001); + RGE_PHY_SETBIT(sc, 0xa442, 0x0080); +} + +static void +rge_phy_config_mcu(struct rge_softc *sc, uint16_t rcodever) +{ + if (sc->rge_rcodever != rcodever) { + int i; + + rge_patch_phy_mcu(sc, 1); + + if (sc->rge_type == MAC_R25) { + rge_write_phy_ocp(sc, 0xa436, 0x8024); + rge_write_phy_ocp(sc, 0xa438, 0x8601); + rge_write_phy_ocp(sc, 0xa436, 0xb82e); + rge_write_phy_ocp(sc, 0xa438, 0x0001); + + RGE_PHY_SETBIT(sc, 0xb820, 0x0080); + + for (i = 0; i < nitems(mac_r25_mcu); i++) + rge_write_phy_ocp(sc, + mac_r25_mcu[i].reg, mac_r25_mcu[i].val); + + RGE_PHY_CLRBIT(sc, 0xb820, 0x0080); + + rge_write_phy_ocp(sc, 0xa436, 0); + rge_write_phy_ocp(sc, 0xa438, 0); + RGE_PHY_CLRBIT(sc, 0xb82e, 0x0001); + rge_write_phy_ocp(sc, 0xa436, 0x8024); + rge_write_phy_ocp(sc, 0xa438, 0); + } else if (sc->rge_type == MAC_R25B) { + for (i = 0; i < nitems(mac_r25b_mcu); i++) + rge_write_phy_ocp(sc, + mac_r25b_mcu[i].reg, mac_r25b_mcu[i].val); + } else if (sc->rge_type == MAC_R25D) { + for (i = 0; i < 2403; i++) + rge_write_phy_ocp(sc, + mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); + rge_patch_phy_mcu(sc, 0); + + rge_patch_phy_mcu(sc, 1); + for (; i < 2528; i++) + rge_write_phy_ocp(sc, + mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); + rge_patch_phy_mcu(sc, 0); + + rge_patch_phy_mcu(sc, 1); + for (; i < nitems(mac_r25d_mcu); i++) + rge_write_phy_ocp(sc, + mac_r25d_mcu[i].reg, mac_r25d_mcu[i].val); + } else if (sc->rge_type == MAC_R26) { + for (i = 0; i < nitems(mac_r26_mcu); i++) + rge_write_phy_ocp(sc, + mac_r26_mcu[i].reg, mac_r26_mcu[i].val); + } else if (sc->rge_type == MAC_R27) { + for (i = 0; i < 1887; i++) + rge_write_phy_ocp(sc, + mac_r27_mcu[i].reg, mac_r27_mcu[i].val); + rge_patch_phy_mcu(sc, 0); + + rge_patch_phy_mcu(sc, 1); + for (; i < nitems(mac_r27_mcu); i++) + rge_write_phy_ocp(sc, + mac_r27_mcu[i].reg, mac_r27_mcu[i].val); + } + + rge_patch_phy_mcu(sc, 0); + + /* Write ram code version. */ + rge_write_phy_ocp(sc, 0xa436, 0x801e); + rge_write_phy_ocp(sc, 0xa438, rcodever); + } +} + +void +rge_set_macaddr(struct rge_softc *sc, const uint8_t *addr) +{ + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_WRITE_4(sc, RGE_MAC0, + addr[3] << 24 | addr[2] << 16 | addr[1] << 8 | addr[0]); + RGE_WRITE_4(sc, RGE_MAC4, + addr[5] << 8 | addr[4]); + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); +} + +/** + * @brief Read the mac address from the NIC EEPROM. + * + * Note this also calls rge_set_macaddr() which programs + * it into the PPROM; I'm not sure why. + * + * Must be called with the driver lock held. + */ +void +rge_get_macaddr(struct rge_softc *sc, uint8_t *addr) +{ + int i; + + RGE_ASSERT_LOCKED(sc); + + for (i = 0; i < ETHER_ADDR_LEN; i++) + addr[i] = RGE_READ_1(sc, RGE_MAC0 + i); + + *(uint32_t *)&addr[0] = RGE_READ_4(sc, RGE_ADDR0); + *(uint16_t *)&addr[4] = RGE_READ_2(sc, RGE_ADDR1); + + rge_set_macaddr(sc, addr); +} + +/** + * @brief MAC hardware initialisation + * + * Must be called with the driver lock held. + */ +static void +rge_hw_init(struct rge_softc *sc) +{ + uint16_t reg; + int i; + + RGE_ASSERT_LOCKED(sc); + + rge_disable_aspm_clkreq(sc); + RGE_CLRBIT_1(sc, 0xf1, 0x80); + + /* Disable UPS. */ + RGE_MAC_CLRBIT(sc, 0xd40a, 0x0010); + + /* Disable MAC MCU. */ + rge_disable_aspm_clkreq(sc); + rge_write_mac_ocp(sc, 0xfc48, 0); + for (reg = 0xfc28; reg < 0xfc48; reg += 2) + rge_write_mac_ocp(sc, reg, 0); + DELAY(3000); + rge_write_mac_ocp(sc, 0xfc26, 0); + + /* Read microcode version. */ + rge_switch_mcu_ram_page(sc, 2); + sc->rge_mcodever = 0; + for (i = 0; i < 8; i += 2) { + sc->rge_mcodever <<= 16; + sc->rge_mcodever |= rge_read_mac_ocp(sc, 0xf9f8 + i); + } + rge_switch_mcu_ram_page(sc, 0); + + rge_mac_config_mcu(sc, sc->rge_type); + + /* Disable PHY power saving. */ + if (sc->rge_type == MAC_R25) + rge_disable_phy_ocp_pwrsave(sc); + + /* Set PCIe uncorrectable error status. */ + rge_write_csi(sc, 0x108, + rge_read_csi(sc, 0x108) | 0x00100000); +} + +void +rge_hw_reset(struct rge_softc *sc) +{ + /* Disable interrupts */ + RGE_WRITE_4(sc, RGE_IMR, 0); + RGE_WRITE_4(sc, RGE_ISR, RGE_READ_4(sc, RGE_ISR)); + + /* Clear timer interrupts. */ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + RGE_WRITE_4(sc, RGE_TIMERINT1, 0); + RGE_WRITE_4(sc, RGE_TIMERINT2, 0); + RGE_WRITE_4(sc, RGE_TIMERINT3, 0); + + rge_reset(sc); +} + +static void +rge_disable_phy_ocp_pwrsave(struct rge_softc *sc) +{ + if (rge_read_phy_ocp(sc, 0xc416) != 0x0500) { + rge_patch_phy_mcu(sc, 1); + rge_write_phy_ocp(sc, 0xc416, 0); + rge_write_phy_ocp(sc, 0xc416, 0x0500); + rge_patch_phy_mcu(sc, 0); + } +} + +static void +rge_patch_phy_mcu(struct rge_softc *sc, int set) +{ + int i; + + if (set) + RGE_PHY_SETBIT(sc, 0xb820, 0x0010); + else + RGE_PHY_CLRBIT(sc, 0xb820, 0x0010); + + for (i = 0; i < 1000; i++) { + if (set) { + if ((rge_read_phy_ocp(sc, 0xb800) & 0x0040) != 0) + break; + } else { + if (!(rge_read_phy_ocp(sc, 0xb800) & 0x0040)) + break; + } + DELAY(100); + } + if (i == 1000) + RGE_PRINT_ERROR(sc, "timeout waiting to patch phy mcu\n"); +} + +void +rge_config_imtype(struct rge_softc *sc, int imtype) +{ + switch (imtype) { + case RGE_IMTYPE_NONE: + sc->rge_intrs = RGE_INTRS; + break; + case RGE_IMTYPE_SIM: + sc->rge_intrs = RGE_INTRS_TIMER; + break; + default: + RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype); + } +} + +void +rge_disable_aspm_clkreq(struct rge_softc *sc) +{ + int unlock = 1; + + if ((RGE_READ_1(sc, RGE_EECMD) & RGE_EECMD_WRITECFG) == + RGE_EECMD_WRITECFG) + unlock = 0; + + if (unlock) + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + if (sc->rge_type == MAC_R26 || sc->rge_type == MAC_R27) + RGE_CLRBIT_1(sc, RGE_INT_CFG0, 0x08); + else + RGE_CLRBIT_1(sc, RGE_CFG2, RGE_CFG2_CLKREQ_EN); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_PME_STS); + + if (unlock) + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); +} + +static void +rge_disable_hw_im(struct rge_softc *sc) +{ + RGE_WRITE_2(sc, RGE_IM, 0); +} + +static void +rge_disable_sim_im(struct rge_softc *sc) +{ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0); + sc->rge_timerintr = 0; +} + +static void +rge_setup_sim_im(struct rge_softc *sc) +{ + RGE_WRITE_4(sc, RGE_TIMERINT0, 0x2600); + RGE_WRITE_4(sc, RGE_TIMERCNT, 1); + sc->rge_timerintr = 1; +} + +void +rge_setup_intr(struct rge_softc *sc, int imtype) +{ + rge_config_imtype(sc, imtype); + + /* Enable interrupts. */ + RGE_WRITE_4(sc, RGE_IMR, sc->rge_intrs); + + switch (imtype) { + case RGE_IMTYPE_NONE: + rge_disable_sim_im(sc); + rge_disable_hw_im(sc); + break; + case RGE_IMTYPE_SIM: + rge_disable_hw_im(sc); + rge_setup_sim_im(sc); + break; + default: + RGE_PRINT_ERROR(sc, "unknown imtype %d", imtype); + } +} + +static void +rge_switch_mcu_ram_page(struct rge_softc *sc, int page) +{ + uint16_t val; + + val = rge_read_mac_ocp(sc, 0xe446) & ~0x0003; + val |= page; + rge_write_mac_ocp(sc, 0xe446, val); +} + +static int +rge_exit_oob(struct rge_softc *sc) +{ + int error, i; + + /* Disable RealWoW. */ + rge_write_mac_ocp(sc, 0xc0bc, 0x00ff); + + if ((error = rge_reset(sc)) != 0) + return error; + + /* Disable OOB. */ + RGE_CLRBIT_1(sc, RGE_MCUCMD, RGE_MCUCMD_IS_OOB); + + RGE_MAC_CLRBIT(sc, 0xe8de, 0x4000); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) + break; + } + + rge_write_mac_ocp(sc, 0xc0aa, 0x07d0); + rge_write_mac_ocp(sc, 0xc0a6, 0x01b5); + rge_write_mac_ocp(sc, 0xc01e, 0x5555); + + for (i = 0; i < 10; i++) { + DELAY(100); + if (RGE_READ_2(sc, RGE_TWICMD) & 0x0200) + break; + } + + if (rge_read_mac_ocp(sc, 0xd42c) & 0x0100) { + for (i = 0; i < RGE_TIMEOUT; i++) { + if ((rge_read_phy_ocp(sc, 0xa420) & 0x0007) == 2) + break; + DELAY(1000); + } + RGE_MAC_CLRBIT(sc, 0xd42c, 0x0100); + if (sc->rge_type != MAC_R25) + RGE_PHY_CLRBIT(sc, 0xa466, 0x0001); + RGE_PHY_CLRBIT(sc, 0xa468, 0x000a); + } + + return 0; +} + +void +rge_write_csi(struct rge_softc *sc, uint32_t reg, uint32_t val) +{ + int i; + + RGE_WRITE_4(sc, RGE_CSIDR, val); + RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | + (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT) | RGE_CSIAR_BUSY); + + for (i = 0; i < 20000; i++) { + DELAY(1); + if (!(RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY)) + break; + } + + DELAY(20); +} + +uint32_t +rge_read_csi(struct rge_softc *sc, uint32_t reg) +{ + int i; + + RGE_WRITE_4(sc, RGE_CSIAR, (reg & RGE_CSIAR_ADDR_MASK) | + (RGE_CSIAR_BYTE_EN << RGE_CSIAR_BYTE_EN_SHIFT)); + + for (i = 0; i < 20000; i++) { + DELAY(1); + if (RGE_READ_4(sc, RGE_CSIAR) & RGE_CSIAR_BUSY) + break; + } + + DELAY(20); + + return (RGE_READ_4(sc, RGE_CSIDR)); +} + +void +rge_write_mac_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + + tmp = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; + tmp += val; + tmp |= RGE_MACOCP_BUSY; + RGE_WRITE_4(sc, RGE_MACOCP, tmp); +} + +uint16_t +rge_read_mac_ocp(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + + val = (reg >> 1) << RGE_MACOCP_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_MACOCP, val); + + return (RGE_READ_4(sc, RGE_MACOCP) & RGE_MACOCP_DATA_MASK); +} + +static void +rge_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + int i; + + tmp = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; + tmp |= RGE_EPHYAR_BUSY | (val & RGE_EPHYAR_DATA_MASK); + RGE_WRITE_4(sc, RGE_EPHYAR, tmp); + + for (i = 0; i < 20000; i++) { + DELAY(1); + if (!(RGE_READ_4(sc, RGE_EPHYAR) & RGE_EPHYAR_BUSY)) + break; + } + + DELAY(20); +} + +static uint16_t +rge_read_ephy(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + int i; + + val = (reg & RGE_EPHYAR_ADDR_MASK) << RGE_EPHYAR_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_EPHYAR, val); + + for (i = 0; i < 20000; i++) { + DELAY(1); + val = RGE_READ_4(sc, RGE_EPHYAR); + if (val & RGE_EPHYAR_BUSY) + break; + } + + DELAY(20); + + return (val & RGE_EPHYAR_DATA_MASK); +} + +static uint16_t +rge_check_ephy_ext_add(struct rge_softc *sc, uint16_t reg) +{ + uint16_t val; + + val = (reg >> 12); + rge_write_ephy(sc, RGE_EPHYAR_EXT_ADDR, val); + + return reg & 0x0fff; +} + +static void +rge_r27_write_ephy(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + rge_write_ephy(sc, rge_check_ephy_ext_add(sc, reg), val); +} + +void +rge_write_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg, uint16_t val) +{ + uint16_t off, phyaddr; + + phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); + phyaddr <<= 4; + + off = addr ? reg : 0x10 + (reg % 8); + + phyaddr += (off - 16) << 1; + + rge_write_phy_ocp(sc, phyaddr, val); +} + +uint16_t +rge_read_phy(struct rge_softc *sc, uint16_t addr, uint16_t reg) +{ + uint16_t off, phyaddr; + + phyaddr = addr ? addr : RGE_PHYBASE + (reg / 8); + phyaddr <<= 4; + + off = addr ? reg : 0x10 + (reg % 8); + + phyaddr += (off - 16) << 1; + + return (rge_read_phy_ocp(sc, phyaddr)); +} + +void +rge_write_phy_ocp(struct rge_softc *sc, uint16_t reg, uint16_t val) +{ + uint32_t tmp; + int i; + + tmp = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; + tmp |= RGE_PHYOCP_BUSY | val; + RGE_WRITE_4(sc, RGE_PHYOCP, tmp); + + for (i = 0; i < 20000; i++) { + DELAY(1); + if (!(RGE_READ_4(sc, RGE_PHYOCP) & RGE_PHYOCP_BUSY)) + break; + } +} + +uint16_t +rge_read_phy_ocp(struct rge_softc *sc, uint16_t reg) +{ + uint32_t val; + int i; + + val = (reg >> 1) << RGE_PHYOCP_ADDR_SHIFT; + RGE_WRITE_4(sc, RGE_PHYOCP, val); + + for (i = 0; i < 20000; i++) { + DELAY(1); + val = RGE_READ_4(sc, RGE_PHYOCP); + if (val & RGE_PHYOCP_BUSY) + break; + } + + return (val & RGE_PHYOCP_DATA_MASK); +} + +int +rge_get_link_status(struct rge_softc *sc) +{ + return ((RGE_READ_2(sc, RGE_PHYSTAT) & RGE_PHYSTAT_LINK) ? 1 : 0); +} + +#if 0 +#ifndef SMALL_KERNEL +int +rge_wol(struct ifnet *ifp, int enable) +{ + struct rge_softc *sc = ifp->if_softc; + + if (enable) { + if (!(RGE_READ_1(sc, RGE_CFG1) & RGE_CFG1_PM_EN)) { + printf("%s: power management is disabled, " + "cannot do WOL\n", sc->sc_dev.dv_xname); + return (ENOTSUP); + } + + } + + rge_iff(sc); + + if (enable) + RGE_MAC_SETBIT(sc, 0xc0b6, 0x0001); + else + RGE_MAC_CLRBIT(sc, 0xc0b6, 0x0001); + + RGE_SETBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + RGE_CLRBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE | RGE_CFG5_WOL_UCAST | + RGE_CFG5_WOL_MCAST | RGE_CFG5_WOL_BCAST); + RGE_CLRBIT_1(sc, RGE_CFG3, RGE_CFG3_WOL_LINK | RGE_CFG3_WOL_MAGIC); + if (enable) + RGE_SETBIT_1(sc, RGE_CFG5, RGE_CFG5_WOL_LANWAKE); + RGE_CLRBIT_1(sc, RGE_EECMD, RGE_EECMD_WRITECFG); + + return (0); +} + +void +rge_wol_power(struct rge_softc *sc) +{ + /* Disable RXDV gate. */ + RGE_CLRBIT_1(sc, RGE_PPSW, 0x08); + DELAY(2000); + + RGE_SETBIT_1(sc, RGE_CFG1, RGE_CFG1_PM_EN); + RGE_SETBIT_1(sc, RGE_CFG2, RGE_CFG2_PMSTS_EN); +} +#endif + +#endif diff --git a/sys/dev/rge/if_rge_microcode.h b/sys/dev/rge/if_rge_microcode.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_microcode.h @@ -0,0 +1,13401 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2025 Kevin Lo + * + * Hardware programming portions from Realtek Semiconductor. + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */ + +#ifndef __IF_RGE_MICROCODE_H__ +#define __IF_RGE_MICROCODE_H__ + +struct rge_hw_regaddr_array { + uint16_t reg; + uint16_t val; +}; + +static const struct rge_hw_regaddr_array rtl8125_mac_bps[] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe012 }, { 0xf804, 0xe022 }, + { 0xf806, 0xe024 }, { 0xf808, 0xe029 }, { 0xf80a, 0xe02b }, + { 0xf80c, 0xe094 }, { 0xf80e, 0xe09d }, { 0xf810, 0xe09f }, + { 0xf812, 0xe0aa }, { 0xf814, 0xe0b5 }, { 0xf816, 0xe0c6 }, + { 0xf818, 0xe0cc }, { 0xf81a, 0xe0d1 }, { 0xf81c, 0xe0d6 }, + { 0xf81e, 0xe0d8 }, { 0xf820, 0xc602 }, { 0xf822, 0xbe00 }, + { 0xf824, 0x0000 }, { 0xf826, 0xc60f }, { 0xf828, 0x73c4 }, + { 0xf82a, 0x49b3 }, { 0xf82c, 0xf106 }, { 0xf82e, 0x73c2 }, + { 0xf830, 0xc608 }, { 0xf832, 0xb406 }, { 0xf834, 0xc609 }, + { 0xf836, 0xff80 }, { 0xf838, 0xc605 }, { 0xf83a, 0xb406 }, + { 0xf83c, 0xc605 }, { 0xf83e, 0xff80 }, { 0xf840, 0x0544 }, + { 0xf842, 0x0568 }, { 0xf844, 0xe906 }, { 0xf846, 0xcde8 }, + { 0xf848, 0xc602 }, { 0xf84a, 0xbe00 }, { 0xf84c, 0x0000 }, + { 0xf84e, 0x48c1 }, { 0xf850, 0x48c2 }, { 0xf852, 0x9c46 }, + { 0xf854, 0xc402 }, { 0xf856, 0xbc00 }, { 0xf858, 0x0a12 }, + { 0xf85a, 0xc602 }, { 0xf85c, 0xbe00 }, { 0xf85e, 0x0eba }, + { 0xf860, 0x1501 }, { 0xf862, 0xf02a }, { 0xf864, 0x1500 }, + { 0xf866, 0xf15d }, { 0xf868, 0xc661 }, { 0xf86a, 0x75c8 }, + { 0xf86c, 0x49d5 }, { 0xf86e, 0xf00a }, { 0xf870, 0x49d6 }, + { 0xf872, 0xf008 }, { 0xf874, 0x49d7 }, { 0xf876, 0xf006 }, + { 0xf878, 0x49d8 }, { 0xf87a, 0xf004 }, { 0xf87c, 0x75d2 }, + { 0xf87e, 0x49d9 }, { 0xf880, 0xf150 }, { 0xf882, 0xc553 }, + { 0xf884, 0x77a0 }, { 0xf886, 0x75c8 }, { 0xf888, 0x4855 }, + { 0xf88a, 0x4856 }, { 0xf88c, 0x4857 }, { 0xf88e, 0x4858 }, + { 0xf890, 0x48da }, { 0xf892, 0x48db }, { 0xf894, 0x49fe }, + { 0xf896, 0xf002 }, { 0xf898, 0x485a }, { 0xf89a, 0x49ff }, + { 0xf89c, 0xf002 }, { 0xf89e, 0x485b }, { 0xf8a0, 0x9dc8 }, + { 0xf8a2, 0x75d2 }, { 0xf8a4, 0x4859 }, { 0xf8a6, 0x9dd2 }, + { 0xf8a8, 0xc643 }, { 0xf8aa, 0x75c0 }, { 0xf8ac, 0x49d4 }, + { 0xf8ae, 0xf033 }, { 0xf8b0, 0x49d0 }, { 0xf8b2, 0xf137 }, + { 0xf8b4, 0xe030 }, { 0xf8b6, 0xc63a }, { 0xf8b8, 0x75c8 }, + { 0xf8ba, 0x49d5 }, { 0xf8bc, 0xf00e }, { 0xf8be, 0x49d6 }, + { 0xf8c0, 0xf00c }, { 0xf8c2, 0x49d7 }, { 0xf8c4, 0xf00a }, + { 0xf8c6, 0x49d8 }, { 0xf8c8, 0xf008 }, { 0xf8ca, 0x75d2 }, + { 0xf8cc, 0x49d9 }, { 0xf8ce, 0xf005 }, { 0xf8d0, 0xc62e }, + { 0xf8d2, 0x75c0 }, { 0xf8d4, 0x49d7 }, { 0xf8d6, 0xf125 }, + { 0xf8d8, 0xc528 }, { 0xf8da, 0x77a0 }, { 0xf8dc, 0xc627 }, + { 0xf8de, 0x75c8 }, { 0xf8e0, 0x4855 }, { 0xf8e2, 0x4856 }, + { 0xf8e4, 0x4857 }, { 0xf8e6, 0x4858 }, { 0xf8e8, 0x48da }, + { 0xf8ea, 0x48db }, { 0xf8ec, 0x49fe }, { 0xf8ee, 0xf002 }, + { 0xf8f0, 0x485a }, { 0xf8f2, 0x49ff }, { 0xf8f4, 0xf002 }, + { 0xf8f6, 0x485b }, { 0xf8f8, 0x9dc8 }, { 0xf8fa, 0x75d2 }, + { 0xf8fc, 0x4859 }, { 0xf8fe, 0x9dd2 }, { 0xf900, 0xc616 }, + { 0xf902, 0x75c0 }, { 0xf904, 0x4857 }, { 0xf906, 0x9dc0 }, + { 0xf908, 0xc613 }, { 0xf90a, 0x75c0 }, { 0xf90c, 0x49da }, + { 0xf90e, 0xf003 }, { 0xf910, 0x49d0 }, { 0xf912, 0xf107 }, + { 0xf914, 0xc60b }, { 0xf916, 0xc50e }, { 0xf918, 0x48d9 }, + { 0xf91a, 0x9dc0 }, { 0xf91c, 0x4859 }, { 0xf91e, 0x9dc0 }, + { 0xf920, 0xc608 }, { 0xf922, 0xc702 }, { 0xf924, 0xbf00 }, + { 0xf926, 0x3ae0 }, { 0xf928, 0xe860 }, { 0xf92a, 0xb400 }, + { 0xf92c, 0xb5d4 }, { 0xf92e, 0xe908 }, { 0xf930, 0xe86c }, + { 0xf932, 0x1200 }, { 0xf934, 0xc409 }, { 0xf936, 0x6780 }, + { 0xf938, 0x48f1 }, { 0xf93a, 0x8f80 }, { 0xf93c, 0xc404 }, + { 0xf93e, 0xc602 }, { 0xf940, 0xbe00 }, { 0xf942, 0x10aa }, + { 0xf944, 0xc010 }, { 0xf946, 0xea7c }, { 0xf948, 0xc602 }, + { 0xf94a, 0xbe00 }, { 0xf94c, 0x0000 }, { 0xf94e, 0x740a }, + { 0xf950, 0x4846 }, { 0xf952, 0x4847 }, { 0xf954, 0x9c0a }, + { 0xf956, 0xc607 }, { 0xf958, 0x74c0 }, { 0xf95a, 0x48c6 }, + { 0xf95c, 0x9cc0 }, { 0xf95e, 0xc602 }, { 0xf960, 0xbe00 }, + { 0xf962, 0x13fe }, { 0xf964, 0xe054 }, { 0xf966, 0x72ca }, + { 0xf968, 0x4826 }, { 0xf96a, 0x4827 }, { 0xf96c, 0x9aca }, + { 0xf96e, 0xc607 }, { 0xf970, 0x72c0 }, { 0xf972, 0x48a6 }, + { 0xf974, 0x9ac0 }, { 0xf976, 0xc602 }, { 0xf978, 0xbe00 }, + { 0xf97a, 0x07dc }, { 0xf97c, 0xe054 }, { 0xf97e, 0xc60f }, + { 0xf980, 0x74c4 }, { 0xf982, 0x49cc }, { 0xf984, 0xf109 }, + { 0xf986, 0xc60c }, { 0xf988, 0x74ca }, { 0xf98a, 0x48c7 }, + { 0xf98c, 0x9cca }, { 0xf98e, 0xc609 }, { 0xf990, 0x74c0 }, + { 0xf992, 0x4846 }, { 0xf994, 0x9cc0 }, { 0xf996, 0xc602 }, + { 0xf998, 0xbe00 }, { 0xf99a, 0x2480 }, { 0xf99c, 0xe092 }, + { 0xf99e, 0xe0c0 }, { 0xf9a0, 0xe054 }, { 0xf9a2, 0x7420 }, + { 0xf9a4, 0x48c0 }, { 0xf9a6, 0x9c20 }, { 0xf9a8, 0x7444 }, + { 0xf9aa, 0xc602 }, { 0xf9ac, 0xbe00 }, { 0xf9ae, 0x12f8 }, + { 0xf9b0, 0x1bff }, { 0xf9b2, 0x46eb }, { 0xf9b4, 0x1bff }, + { 0xf9b6, 0xc102 }, { 0xf9b8, 0xb900 }, { 0xf9ba, 0x0d5a }, + { 0xf9bc, 0x1bff }, { 0xf9be, 0x46eb }, { 0xf9c0, 0x1bff }, + { 0xf9c2, 0xc102 }, { 0xf9c4, 0xb900 }, { 0xf9c6, 0x0e2a }, + { 0xf9c8, 0xc602 }, { 0xf9ca, 0xbe00 }, { 0xf9cc, 0x0000 }, + { 0xf9ce, 0xc602 }, { 0xf9d0, 0xbe00 }, { 0xf9d2, 0x0000 }, + { 0xf9d4, 0x0000 }, { 0xf9d6, 0x0000 }, { 0xf9d8, 0x0000 }, + { 0xf9da, 0x0000 }, { 0xf9dc, 0x0000 }, { 0xf9de, 0x0000 }, + { 0xf9e0, 0x0000 }, { 0xf9e2, 0x0000 }, { 0xf9e4, 0x0000 }, + { 0xf9e6, 0x0000 }, { 0xf9e8, 0x0000 }, { 0xf9ea, 0x0000 }, + { 0xf9ec, 0x0000 }, { 0xf9ee, 0x0000 }, { 0xf9f0, 0x0000 }, + { 0xf9f2, 0x0000 }, { 0xf9f4, 0x0000 }, { 0xf9f6, 0x0000 }, + { 0xf9f8, 0x0000 }, { 0xf9fa, 0x0000 }, { 0xf9fc, 0x0000 }, + { 0xf9fe, 0x0000 } +}; + +static const struct rge_hw_regaddr_array rtl8125b_mac_bps[] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe01b }, { 0xf804, 0xe026 }, + { 0xf806, 0xe037 }, { 0xf808, 0xe03d }, { 0xf80a, 0xe057 }, + { 0xf80c, 0xe05b }, { 0xf80e, 0xe060 }, { 0xf810, 0xe062 }, + { 0xf812, 0xe064 }, { 0xf814, 0xe066 }, { 0xf816, 0xe068 }, + { 0xf818, 0xe06a }, { 0xf81a, 0xe06c }, { 0xf81c, 0xe06e }, + { 0xf81e, 0xe070 }, { 0xf820, 0x740a }, { 0xf822, 0x4846 }, + { 0xf824, 0x4847 }, { 0xf826, 0x9c0a }, { 0xf828, 0xc607 }, + { 0xf82a, 0x74c0 }, { 0xf82c, 0x48c6 }, { 0xf82e, 0x9cc0 }, + { 0xf830, 0xc602 }, { 0xf832, 0xbe00 }, { 0xf834, 0x13f0 }, + { 0xf836, 0xe054 }, { 0xf838, 0x72ca }, { 0xf83a, 0x4826 }, + { 0xf83c, 0x4827 }, { 0xf83e, 0x9aca }, { 0xf840, 0xc607 }, + { 0xf842, 0x72c0 }, { 0xf844, 0x48a6 }, { 0xf846, 0x9ac0 }, + { 0xf848, 0xc602 }, { 0xf84a, 0xbe00 }, { 0xf84c, 0x081c }, + { 0xf84e, 0xe054 }, { 0xf850, 0xc60f }, { 0xf852, 0x74c4 }, + { 0xf854, 0x49cc }, { 0xf856, 0xf109 }, { 0xf858, 0xc60c }, + { 0xf85a, 0x74ca }, { 0xf85c, 0x48c7 }, { 0xf85e, 0x9cca }, + { 0xf860, 0xc609 }, { 0xf862, 0x74c0 }, { 0xf864, 0x4846 }, + { 0xf866, 0x9cc0 }, { 0xf868, 0xc602 }, { 0xf86a, 0xbe00 }, + { 0xf86c, 0x2494 }, { 0xf86e, 0xe092 }, { 0xf870, 0xe0c0 }, + { 0xf872, 0xe054 }, { 0xf874, 0x7420 }, { 0xf876, 0x48c0 }, + { 0xf878, 0x9c20 }, { 0xf87a, 0x7444 }, { 0xf87c, 0xc602 }, + { 0xf87e, 0xbe00 }, { 0xf880, 0x12dc }, { 0xf882, 0x733a }, + { 0xf884, 0x21b5 }, { 0xf886, 0x25bc }, { 0xf888, 0x1304 }, + { 0xf88a, 0xf111 }, { 0xf88c, 0x1b12 }, { 0xf88e, 0x1d2a }, + { 0xf890, 0x3168 }, { 0xf892, 0x3ada }, { 0xf894, 0x31ab }, + { 0xf896, 0x1a00 }, { 0xf898, 0x9ac0 }, { 0xf89a, 0x1300 }, + { 0xf89c, 0xf1fb }, { 0xf89e, 0x7620 }, { 0xf8a0, 0x236e }, + { 0xf8a2, 0x276f }, { 0xf8a4, 0x1a3c }, { 0xf8a6, 0x22a1 }, + { 0xf8a8, 0x41b5 }, { 0xf8aa, 0x9ee2 }, { 0xf8ac, 0x76e4 }, + { 0xf8ae, 0x486f }, { 0xf8b0, 0x9ee4 }, { 0xf8b2, 0xc602 }, + { 0xf8b4, 0xbe00 }, { 0xf8b6, 0x4a26 }, { 0xf8b8, 0x733a }, + { 0xf8ba, 0x49bb }, { 0xf8bc, 0xc602 }, { 0xf8be, 0xbe00 }, + { 0xf8c0, 0x47a2 }, { 0xf8c2, 0x48c1 }, { 0xf8c4, 0x48c2 }, + { 0xf8c6, 0x9c46 }, { 0xf8c8, 0xc402 }, { 0xf8ca, 0xbc00 }, + { 0xf8cc, 0x0a52 }, { 0xf8ce, 0xc602 }, { 0xf8d0, 0xbe00 }, + { 0xf8d2, 0x0000 }, { 0xf8d4, 0xc602 }, { 0xf8d6, 0xbe00 }, + { 0xf8d8, 0x0000 }, { 0xf8da, 0xc602 }, { 0xf8dc, 0xbe00 }, + { 0xf8de, 0x0000 }, { 0xf8e0, 0xc602 }, { 0xf8e2, 0xbe00 }, + { 0xf8e4, 0x0000 }, { 0xf8e6, 0xc602 }, { 0xf8e8, 0xbe00 }, + { 0xf8ea, 0x0000 }, { 0xf8ec, 0xc602 }, { 0xf8ee, 0xbe00 }, + { 0xf8f0, 0x0000 }, { 0xf8f2, 0xc602 }, { 0xf8f4, 0xbe00 }, + { 0xf8f6, 0x0000 }, { 0xf8f8, 0xc602 }, { 0xf8fa, 0xbe00 }, + { 0xf8fc, 0x0000 }, { 0xf8fe, 0xc602 }, { 0xf900, 0xbe00 }, + { 0xf902, 0x0000 }, { 0xfc26, 0x8000 }, { 0xfc28, 0x13e6 }, + { 0xfc2a, 0x0812 }, { 0xfc2c, 0x248c }, { 0xfc2e, 0x12da }, + { 0xfc30, 0x4a20 }, { 0xfc32, 0x47a0 }, { 0xfc48, 0x003f } +}; + +static const struct rge_hw_regaddr_array rtl8127_mac_bps[] = { + { 0xf800, 0xe010 }, { 0xf802, 0xe023 }, { 0xf804, 0xe036 }, + { 0xf806, 0xe049 }, { 0xf808, 0xe05c }, { 0xf80a, 0xe075 }, + { 0xf80c, 0xe0b1 }, { 0xf80e, 0xe117 }, { 0xf810, 0xe11b }, + { 0xf812, 0xe11d }, { 0xf814, 0xe11f }, { 0xf816, 0xe121 }, + { 0xf818, 0xe123 }, { 0xf81a, 0xe125 }, { 0xf81c, 0xe127 }, + { 0xf81e, 0xe129 }, { 0xf820, 0x7020 }, { 0xf822, 0xb405 }, + { 0xf824, 0xb404 }, { 0xf826, 0xc50f }, { 0xf828, 0x74a0 }, + { 0xf82a, 0xc50e }, { 0xf82c, 0x4025 }, { 0xf82e, 0xf005 }, + { 0xf830, 0x4850 }, { 0xf832, 0x4025 }, { 0xf834, 0xf002 }, + { 0xf836, 0xe002 }, { 0xf838, 0x4809 }, { 0xf83a, 0xb004 }, + { 0xf83c, 0xb005 }, { 0xf83e, 0xc502 }, { 0xf840, 0xbd00 }, + { 0xf842, 0x1522 }, { 0xf844, 0xd006 }, { 0xf846, 0x0004 }, + { 0xf848, 0x7760 }, { 0xf84a, 0xb405 }, { 0xf84c, 0xb404 }, + { 0xf84e, 0xc50f }, { 0xf850, 0x74a0 }, { 0xf852, 0xc50e }, + { 0xf854, 0x4025 }, { 0xf856, 0xf005 }, { 0xf858, 0x4850 }, + { 0xf85a, 0x4025 }, { 0xf85c, 0xf002 }, { 0xf85e, 0xe002 }, + { 0xf860, 0x4879 }, { 0xf862, 0xb004 }, { 0xf864, 0xb005 }, + { 0xf866, 0xc002 }, { 0xf868, 0xb800 }, { 0xf86a, 0x41e2 }, + { 0xf86c, 0xd006 }, { 0xf86e, 0x0004 }, { 0xf870, 0x7160 }, + { 0xf872, 0xb405 }, { 0xf874, 0xb404 }, { 0xf876, 0xc50f }, + { 0xf878, 0x74a0 }, { 0xf87a, 0xc50e }, { 0xf87c, 0x4025 }, + { 0xf87e, 0xf005 }, { 0xf880, 0x4850 }, { 0xf882, 0x4025 }, + { 0xf884, 0xf002 }, { 0xf886, 0xe002 }, { 0xf888, 0x4819 }, + { 0xf88a, 0xb004 }, { 0xf88c, 0xb005 }, { 0xf88e, 0xc302 }, + { 0xf890, 0xbb00 }, { 0xf892, 0x508e }, { 0xf894, 0xd006 }, + { 0xf896, 0x0004 }, { 0xf898, 0x7720 }, { 0xf89a, 0xb405 }, + { 0xf89c, 0xb404 }, { 0xf89e, 0xc50f }, { 0xf8a0, 0x74a0 }, + { 0xf8a2, 0xc50e }, { 0xf8a4, 0x4025 }, { 0xf8a6, 0xf005 }, + { 0xf8a8, 0x4850 }, { 0xf8aa, 0x4025 }, { 0xf8ac, 0xf002 }, + { 0xf8ae, 0xe002 }, { 0xf8b0, 0x4879 }, { 0xf8b2, 0xb004 }, + { 0xf8b4, 0xb005 }, { 0xf8b6, 0xc102 }, { 0xf8b8, 0xb900 }, + { 0xf8ba, 0x50f8 }, { 0xf8bc, 0xd006 }, { 0xf8be, 0x0004 }, + { 0xf8c0, 0x61a9 }, { 0xf8c2, 0xb403 }, { 0xf8c4, 0xb404 }, + { 0xf8c6, 0xc313 }, { 0xf8c8, 0x7460 }, { 0xf8ca, 0xc312 }, + { 0xf8cc, 0x4023 }, { 0xf8ce, 0xf005 }, { 0xf8d0, 0x4830 }, + { 0xf8d2, 0x4023 }, { 0xf8d4, 0xf002 }, { 0xf8d6, 0xe003 }, + { 0xf8d8, 0x4997 }, { 0xf8da, 0xf003 }, { 0xf8dc, 0xc00a }, + { 0xf8de, 0xe002 }, { 0xf8e0, 0xc009 }, { 0xf8e2, 0xb004 }, + { 0xf8e4, 0xb003 }, { 0xf8e6, 0xc102 }, { 0xf8e8, 0xb900 }, + { 0xf8ea, 0x34fc }, { 0xf8ec, 0xd006 }, { 0xf8ee, 0x0004 }, + { 0xf8f0, 0x02af }, { 0xf8f2, 0x041f }, { 0xf8f4, 0xb407 }, + { 0xf8f6, 0xb406 }, { 0xf8f8, 0xb405 }, { 0xf8fa, 0xb404 }, + { 0xf8fc, 0xb403 }, { 0xf8fe, 0xb402 }, { 0xf900, 0xb401 }, + { 0xf902, 0xb400 }, { 0xf904, 0x49d2 }, { 0xf906, 0xf116 }, + { 0xf908, 0xc62f }, { 0xf90a, 0x77c0 }, { 0xf90c, 0x49f9 }, + { 0xf90e, 0xf020 }, { 0xf910, 0x49fa }, { 0xf912, 0xf11e }, + { 0xf914, 0x49f2 }, { 0xf916, 0xf102 }, { 0xf918, 0xe01b }, + { 0xf91a, 0x48f2 }, { 0xf91c, 0x9fc0 }, { 0xf91e, 0xc625 }, + { 0xf920, 0x75c2 }, { 0xf922, 0x4852 }, { 0xf924, 0x9dc2 }, + { 0xf926, 0xc122 }, { 0xf928, 0x7020 }, { 0xf92a, 0x4801 }, + { 0xf92c, 0x4802 }, { 0xf92e, 0x9820 }, { 0xf930, 0xe00f }, + { 0xf932, 0xc61a }, { 0xf934, 0x77c0 }, { 0xf936, 0x49f2 }, + { 0xf938, 0xf10b }, { 0xf93a, 0xc618 }, { 0xf93c, 0x77c0 }, + { 0xf93e, 0x49f2 }, { 0xf940, 0xf007 }, { 0xf942, 0x48f2 }, + { 0xf944, 0x9fc0 }, { 0xf946, 0xc611 }, { 0xf948, 0x75c2 }, + { 0xf94a, 0x48d2 }, { 0xf94c, 0x9dc2 }, { 0xf94e, 0xb000 }, + { 0xf950, 0xb001 }, { 0xf952, 0xb002 }, { 0xf954, 0xb003 }, + { 0xf956, 0xb004 }, { 0xf958, 0xb005 }, { 0xf95a, 0xb006 }, + { 0xf95c, 0xb007 }, { 0xf95e, 0x9d6c }, { 0xf960, 0xc502 }, + { 0xf962, 0xbd00 }, { 0xf964, 0x0168 }, { 0xf966, 0xe024 }, + { 0xf968, 0xc010 }, { 0xf96a, 0xd410 }, { 0xf96c, 0xd460 }, + { 0xf96e, 0xb407 }, { 0xf970, 0xb406 }, { 0xf972, 0xb405 }, + { 0xf974, 0xb404 }, { 0xf976, 0xb403 }, { 0xf978, 0xb402 }, + { 0xf97a, 0xb401 }, { 0xf97c, 0xb400 }, { 0xf97e, 0xc152 }, + { 0xf980, 0x7020 }, { 0xf982, 0x4981 }, { 0xf984, 0xf043 }, + { 0xf986, 0xc050 }, { 0xf988, 0x7100 }, { 0xf98a, 0xb401 }, + { 0xf98c, 0xc14c }, { 0xf98e, 0x489e }, { 0xf990, 0x481d }, + { 0xf992, 0x9900 }, { 0xf994, 0xc24a }, { 0xf996, 0x7340 }, + { 0xf998, 0x49b7 }, { 0xf99a, 0xf135 }, { 0xf99c, 0xc144 }, + { 0xf99e, 0x9900 }, { 0xf9a0, 0xc245 }, { 0xf9a2, 0x7340 }, + { 0xf9a4, 0xc447 }, { 0xf9a6, 0x401c }, { 0xf9a8, 0xf109 }, + { 0xf9aa, 0x734c }, { 0xf9ac, 0x1301 }, { 0xf9ae, 0xf12b }, + { 0xf9b0, 0xc343 }, { 0xf9b2, 0x9b40 }, { 0xf9b4, 0xc33e }, + { 0xf9b6, 0x9b40 }, { 0xf9b8, 0xe022 }, { 0xf9ba, 0xc63a }, + { 0xf9bc, 0x77c0 }, { 0xf9be, 0x48f4 }, { 0xf9c0, 0x48f5 }, + { 0xf9c2, 0x48f9 }, { 0xf9c4, 0x48fa }, { 0xf9c6, 0x9fc0 }, + { 0xf9c8, 0xc231 }, { 0xf9ca, 0x7344 }, { 0xf9cc, 0x48b4 }, + { 0xf9ce, 0x9b44 }, { 0xf9d0, 0xc22e }, { 0xf9d2, 0x7340 }, + { 0xf9d4, 0x4830 }, { 0xf9d6, 0x48b1 }, { 0xf9d8, 0x4832 }, + { 0xf9da, 0x483c }, { 0xf9dc, 0x48bd }, { 0xf9de, 0x48be }, + { 0xf9e0, 0x48bf }, { 0xf9e2, 0x9b40 }, { 0xf9e4, 0xc223 }, + { 0xf9e6, 0xc32a }, { 0xf9e8, 0x9b48 }, { 0xf9ea, 0xc327 }, + { 0xf9ec, 0x9b46 }, { 0xf9ee, 0xc324 }, { 0xf9f0, 0x9b40 }, + { 0xf9f2, 0xc321 }, { 0xf9f4, 0x9b42 }, { 0xf9f6, 0xc31e }, + { 0xf9f8, 0x9b40 }, { 0xf9fa, 0xe005 }, { 0xf9fc, 0xc113 }, + { 0xf9fe, 0x7020 }, { 0xf800, 0x4881 }, { 0xf802, 0x9820 }, + { 0xf804, 0xb001 }, { 0xf806, 0xc010 }, { 0xf808, 0x9900 }, + { 0xf80a, 0xb000 }, { 0xf80c, 0xb001 }, { 0xf80e, 0xb002 }, + { 0xf810, 0xb003 }, { 0xf812, 0xb004 }, { 0xf814, 0xb005 }, + { 0xf816, 0xb006 }, { 0xf818, 0xb007 }, { 0xf81a, 0x2125 }, + { 0xf81c, 0xc102 }, { 0xf81e, 0xb900 }, { 0xf820, 0x1a6c }, + { 0xf822, 0xd410 }, { 0xf824, 0xc000 }, { 0xf826, 0xe86c }, + { 0xf828, 0xb600 }, { 0xf82a, 0xb800 }, { 0xf82c, 0xb40a }, + { 0xf82e, 0xe024 }, { 0xf830, 0x5a00 }, { 0xf832, 0x5a81 }, + { 0xf834, 0x0073 }, { 0xf836, 0x5a80 }, { 0xf838, 0x0042 }, + { 0xf83a, 0x0001 }, { 0xf83c, 0xc104 }, { 0xf83e, 0xc202 }, + { 0xf840, 0xba00 }, { 0xf842, 0x1a2e }, { 0xf844, 0xc896 }, + { 0xf846, 0xc302 }, { 0xf848, 0xbb00 }, { 0xf84a, 0x0000 }, + { 0xf84c, 0xc002 }, { 0xf84e, 0xb800 }, { 0xf850, 0x0000 }, + { 0xf852, 0xc002 }, { 0xf854, 0xb800 }, { 0xf856, 0x0000 }, + { 0xf858, 0xc502 }, { 0xf85a, 0xbd00 }, { 0xf85c, 0x0000 }, + { 0xf85e, 0xc102 }, { 0xf860, 0xb900 }, { 0xf862, 0x0000 }, + { 0xf864, 0xc102 }, { 0xf866, 0xb900 }, { 0xf868, 0x0000 }, + { 0xf86a, 0xc602 }, { 0xf86c, 0xbe00 }, { 0xf86e, 0x0000 }, + { 0xf870, 0xc602 }, { 0xf872, 0xbe00 }, { 0xf874, 0x0000 }, + { 0xf876, 0x6961 }, { 0xf878, 0x0019 }, { 0xf87a, 0x050c }, + { 0xf87c, 0x140c } +}; + +static const struct rge_hw_regaddr_array mac_r25_ephy[] = { + { 0x0004, 0xd000 }, { 0x000a, 0x8653 }, { 0x0023, 0xab66 }, + { 0x0020, 0x9455 }, { 0x0021, 0x99ff }, { 0x0029, 0xfe04 }, + { 0x0044, 0xd000 }, { 0x004a, 0x8653 }, { 0x0063, 0xab66 }, + { 0x0060, 0x9455 }, { 0x0061, 0x99ff }, { 0x0069, 0xfe04 } +}; + +static const struct rge_hw_regaddr_array mac_r25b_ephy[] = { + { 0x000b, 0xa908 }, { 0x001e, 0x20eb }, { 0x0022, 0x0023 }, + { 0x0002, 0x60c2 }, { 0x0029, 0xff00 }, { 0x004b, 0xa908 }, + { 0x005e, 0x28eb }, { 0x0062, 0x0023 }, { 0x0042, 0x60c2 }, + { 0x0069, 0xff00 } +}; + +static const struct rge_hw_regaddr_array mac_r27_ephy[] = { + { 0x8088, 0x0064 }, { 0x8488, 0x0064 }, { 0x8888, 0x0064 }, + { 0x8c88, 0x0064 }, { 0x8188, 0x0064 }, { 0x8588, 0x0064 }, + { 0x8988, 0x0064 }, { 0x8d88, 0x0064 }, { 0x808c, 0x09b0 }, + { 0x848c, 0x09b0 }, { 0x888c, 0x0f90 }, { 0x8c8c, 0x0f90 }, + { 0x818c, 0x09b0 }, { 0x858c, 0x09b0 }, { 0x898c, 0x0f90 }, + { 0x8d8c, 0x0f90 }, { 0x808a, 0x09b8 }, { 0x848a, 0x09b8 }, + { 0x888a, 0x0f98 }, { 0x8c8a, 0x0f98 }, { 0x818a, 0x09b8 }, + { 0x858a, 0x09b8 }, { 0x898a, 0x0f98 }, { 0x8d8a, 0x0f98 }, + { 0x9020, 0x0080 }, { 0x9420, 0x0080 }, { 0x9820, 0x0080 }, + { 0x9c20, 0x0080 }, { 0x901e, 0x0190 }, { 0x941e, 0x0190 }, + { 0x981e, 0x0140 }, { 0x9c1e, 0x0140 }, { 0x901c, 0x0190 }, + { 0x941c, 0x0190 }, { 0x981c, 0x0140 }, { 0x9c1c, 0x0140 } +}; + +static const struct rge_hw_regaddr_array mac_r27_mcu[] = { + { 0xa436, 0x8023 }, { 0xa438, 0x6100 }, { 0xa436, 0xb82e }, + { 0xa438, 0x0001 }, { 0xb820, 0x0090 }, { 0xa436, 0xa016 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, + { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0x1800 }, + { 0xa438, 0x801a }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, + { 0xa438, 0x1800 }, { 0xa438, 0x801a }, { 0xa438, 0xce00 }, + { 0xa438, 0x2941 }, { 0xa438, 0x8017 }, { 0xa438, 0x2c59 }, + { 0xa438, 0x8017 }, { 0xa438, 0x1800 }, { 0xa438, 0x0e11 }, + { 0xa438, 0x8aff }, { 0xa438, 0x1800 }, { 0xa438, 0x0e11 }, + { 0xa436, 0xa026 }, { 0xa438, 0xffff }, { 0xa436, 0xa024 }, + { 0xa438, 0xffff }, { 0xa436, 0xa022 }, { 0xa438, 0xffff }, + { 0xa436, 0xa020 }, { 0xa438, 0xffff }, { 0xa436, 0xa006 }, + { 0xa438, 0xffff }, { 0xa436, 0xa004 }, { 0xa438, 0xffff }, + { 0xa436, 0xa002 }, { 0xa438, 0xffff }, { 0xa436, 0xa000 }, + { 0xa438, 0x0e10 }, { 0xa436, 0xa008 }, { 0xa438, 0x0100 }, + { 0xa436, 0xa016 }, { 0xa438, 0x0000 }, { 0xa436, 0xa012 }, + { 0xa438, 0x0ff8 }, { 0xa436, 0xa014 }, { 0xa438, 0x219a }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa436, 0xa152 }, { 0xa438, 0x21a4 }, + { 0xa436, 0xa154 }, { 0xa438, 0x3fff }, { 0xa436, 0xa156 }, + { 0xa438, 0x3fff }, { 0xa436, 0xa158 }, { 0xa438, 0x3fff }, + { 0xa436, 0xa15a }, { 0xa438, 0x3fff }, { 0xa436, 0xa15c }, + { 0xa438, 0x3fff }, { 0xa436, 0xa15e }, { 0xa438, 0x3fff }, + { 0xa436, 0xa160 }, { 0xa438, 0x3fff }, { 0xa436, 0xa150 }, + { 0xa438, 0x0001 }, { 0xa436, 0xa016 }, { 0xa438, 0x0010 }, + { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, { 0xa436, 0xa014 }, + { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, { 0xa438, 0x1800 }, + { 0xa438, 0x8014 }, { 0xa438, 0x1800 }, { 0xa438, 0x801a }, + { 0xa438, 0x1800 }, { 0xa438, 0x801e }, { 0xa438, 0x1800 }, + { 0xa438, 0x8026 }, { 0xa438, 0x1800 }, { 0xa438, 0x802e }, + { 0xa438, 0x1800 }, { 0xa438, 0x8036 }, { 0xa438, 0x1800 }, + { 0xa438, 0x803a }, { 0xa438, 0xce01 }, { 0xa438, 0x8208 }, + { 0xa438, 0x1800 }, { 0xa438, 0x0028 }, { 0xa438, 0x1000 }, + { 0xa438, 0x02c5 }, { 0xa438, 0x1000 }, { 0xa438, 0x0304 }, + { 0xa438, 0x1800 }, { 0xa438, 0x0119 }, { 0xa438, 0xce01 }, + { 0xa438, 0x8208 }, { 0xa438, 0x1800 }, { 0xa438, 0x009e }, + { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, { 0xa438, 0xa50f }, + { 0xa438, 0x8208 }, { 0xa438, 0xd500 }, { 0xa438, 0xaa0f }, + { 0xa438, 0x1800 }, { 0xa438, 0x015b }, { 0xa438, 0xd501 }, + { 0xa438, 0xce01 }, { 0xa438, 0xa50f }, { 0xa438, 0x8208 }, + { 0xa438, 0xd500 }, { 0xa438, 0xaa0f }, { 0xa438, 0x1800 }, + { 0xa438, 0x01a9 }, { 0xa438, 0xd501 }, { 0xa438, 0xce01 }, + { 0xa438, 0xa50f }, { 0xa438, 0x8208 }, { 0xa438, 0xd500 }, + { 0xa438, 0xaa0f }, { 0xa438, 0x1800 }, { 0xa438, 0x01f4 }, + { 0xa438, 0x8208 }, { 0xa438, 0xd500 }, { 0xa438, 0x1800 }, + { 0xa438, 0x02a5 }, { 0xa438, 0xa208 }, { 0xa438, 0xd500 }, + { 0xa438, 0x1800 }, { 0xa438, 0x02b8 }, { 0xa436, 0xa08e }, + { 0xa438, 0x02b7 }, { 0xa436, 0xa08c }, { 0xa438, 0x02a4 }, + { 0xa436, 0xa08a }, { 0xa438, 0x01e7 }, { 0xa436, 0xa088 }, + { 0xa438, 0x019c }, { 0xa436, 0xa086 }, { 0xa438, 0x014e }, + { 0xa436, 0xa084 }, { 0xa438, 0x009d }, { 0xa436, 0xa082 }, + { 0xa438, 0x0117 }, { 0xa436, 0xa080 }, { 0xa438, 0x0027 }, + { 0xa436, 0xa090 }, { 0xa438, 0x00ff }, { 0xa436, 0xa016 }, + { 0xa438, 0x0020 }, { 0xa436, 0xa012 }, { 0xa438, 0x0000 }, + { 0xa436, 0xa014 }, { 0xa438, 0x1800 }, { 0xa438, 0x8010 }, + { 0xa438, 0x1800 }, { 0xa438, 0x801d }, { 0xa438, 0x1800 }, + { 0xa438, 0x803b }, { 0xa438, 0x1800 }, { 0xa438, 0x8087 }, + { 0xa438, 0x1800 }, { 0xa438, 0x808e }, { 0xa438, 0x1800 }, + { 0xa438, 0x809d }, { 0xa438, 0x1800 }, { 0xa438, 0x80b7 }, + { 0xa438, 0x1800 }, { 0xa438, 0x80c4 }, { 0xa438, 0xd1bc }, + { 0xa438, 0xd040 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0xd700 }, + { 0xa438, 0x273d }, { 0xa438, 0x801b }, { 0xa438, 0x1800 }, + { 0xa438, 0x07d1 }, { 0xa438, 0x1800 }, { 0xa438, 0x080e }, + { 0xa438, 0xd700 }, { 0xa438, 0x37c9 }, { 0xa438, 0x8032 }, + { 0xa438, 0x33a9 }, { 0xa438, 0x802a }, { 0xa438, 0xd705 }, + { 0xa438, 0x4084 }, { 0xa438, 0xd1f4 }, { 0xa438, 0xd048 }, + { 0xa438, 0xf013 }, { 0xa438, 0xd1b7 }, { 0xa438, 0xd04b }, + { 0xa438, 0xf010 }, { 0xa438, 0xd705 }, { 0xa438, 0x4084 }, + { 0xa438, 0xd1f4 }, { 0xa438, 0xd048 }, { 0xa438, 0xf00b }, + { 0xa438, 0xd1b7 }, { 0xa438, 0xd04b }, { 0xa438, 0xf008 }, + { 0xa438, 0xd705 }, { 0xa438, 0x4084 }, { 0xa438, 0xd1f4 }, + { 0xa438, 0xd048 }, { 0xa438, 0xf003 }, { 0xa438, 0xd1b7 }, + { 0xa438, 0xd04b }, { 0xa438, 0x1800 }, { 0xa438, 0x14cc }, + { 0xa438, 0xd700 }, { 0xa438, 0x2b59 }, { 0xa438, 0x803f }, + { 0xa438, 0xf003 }, { 0xa438, 0x1800 }, { 0xa438, 0x118f }, + { 0xa438, 0x6060 }, { 0xa438, 0x1800 }, { 0xa438, 0x1167 }, + { 0xa438, 0xd700 }, { 0xa438, 0x60c7 }, { 0xa438, 0xd704 }, + { 0xa438, 0x609f }, { 0xa438, 0xd705 }, { 0xa438, 0x4043 }, + { 0xa438, 0xf003 }, { 0xa438, 0x1800 }, { 0xa438, 0x1150 }, + { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, { 0xa438, 0x8702 }, + { 0xa438, 0x8011 }, { 0xa438, 0x9503 }, { 0xa438, 0x800a }, + { 0xa438, 0x81a0 }, { 0xa438, 0x8302 }, { 0xa438, 0x8480 }, + { 0xa438, 0x8686 }, { 0xa438, 0xcde0 }, { 0xa438, 0xd1ff }, + { 0xa438, 0xd049 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0xd705 }, + { 0xa438, 0x417e }, { 0xa438, 0x0c03 }, { 0xa438, 0x1502 }, + { 0xa438, 0xa011 }, { 0xa438, 0x9503 }, { 0xa438, 0xd1c8 }, + { 0xa438, 0xd045 }, { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, + { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0xa702 }, { 0xa438, 0x9503 }, + { 0xa438, 0xa00a }, { 0xa438, 0xa1a0 }, { 0xa438, 0xa480 }, + { 0xa438, 0xa686 }, { 0xa438, 0xd705 }, { 0xa438, 0x605e }, + { 0xa438, 0xa302 }, { 0xa438, 0x9503 }, { 0xa438, 0xd700 }, + { 0xa438, 0x37c9 }, { 0xa438, 0x8083 }, { 0xa438, 0x33a9 }, + { 0xa438, 0x807f }, { 0xa438, 0xd178 }, { 0xa438, 0xd04b }, + { 0xa438, 0x1800 }, { 0xa438, 0x115d }, { 0xa438, 0xd1c8 }, + { 0xa438, 0xd04b }, { 0xa438, 0x1800 }, { 0xa438, 0x115d }, + { 0xa438, 0xd1e6 }, { 0xa438, 0xd04b }, { 0xa438, 0x1800 }, + { 0xa438, 0x115d }, { 0xa438, 0xd71f }, { 0xa438, 0x6080 }, + { 0xa438, 0xd704 }, { 0xa438, 0x1800 }, { 0xa438, 0x1bc0 }, + { 0xa438, 0x1800 }, { 0xa438, 0x1bc4 }, { 0xa438, 0x4134 }, + { 0xa438, 0xd115 }, { 0xa438, 0xd04f }, { 0xa438, 0x1000 }, + { 0xa438, 0x1d0b }, { 0xa438, 0x1000 }, { 0xa438, 0x80ad }, + { 0xa438, 0x1800 }, { 0xa438, 0x01f2 }, { 0xa438, 0x1000 }, + { 0xa438, 0x1d0b }, { 0xa438, 0x1000 }, { 0xa438, 0x80ad }, + { 0xa438, 0x1800 }, { 0xa438, 0x01f9 }, { 0xa438, 0x2969 }, + { 0xa438, 0x80a3 }, { 0xa438, 0xd700 }, { 0xa438, 0x606b }, + { 0xa438, 0xd701 }, { 0xa438, 0x60b4 }, { 0xa438, 0x1000 }, + { 0xa438, 0x80ad }, { 0xa438, 0x1800 }, { 0xa438, 0x0551 }, + { 0xa438, 0xd196 }, { 0xa438, 0xd04d }, { 0xa438, 0x1000 }, + { 0xa438, 0x80ad }, { 0xa438, 0x1800 }, { 0xa438, 0x054d }, + { 0xa438, 0xd208 }, { 0xa438, 0x0c09 }, { 0xa438, 0x1301 }, + { 0xa438, 0x1000 }, { 0xa438, 0x1cd2 }, { 0xa438, 0xd701 }, + { 0xa438, 0x5fa3 }, { 0xa438, 0xb302 }, { 0xa438, 0xd200 }, + { 0xa438, 0x0800 }, { 0xa438, 0xd705 }, { 0xa438, 0x6064 }, + { 0xa438, 0x1800 }, { 0xa438, 0x140a }, { 0xa438, 0x8810 }, + { 0xa438, 0xd199 }, { 0xa438, 0xd04b }, { 0xa438, 0x1000 }, + { 0xa438, 0x1cd2 }, { 0xa438, 0xd700 }, { 0xa438, 0x5fba }, + { 0xa438, 0x1800 }, { 0xa438, 0x140a }, { 0xa438, 0x8910 }, + { 0xa438, 0xd704 }, { 0xa438, 0x61a8 }, { 0xa438, 0x8480 }, + { 0xa438, 0x8604 }, { 0xa438, 0x8302 }, { 0xa438, 0x81a0 }, + { 0xa438, 0xd703 }, { 0xa438, 0x4112 }, { 0xa438, 0x0c03 }, + { 0xa438, 0x1502 }, { 0xa438, 0xa990 }, { 0xa438, 0x9503 }, + { 0xa438, 0xb904 }, { 0xa438, 0xf002 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0800 }, { 0xa436, 0xa10e }, { 0xa438, 0x1de8 }, + { 0xa436, 0xa10c }, { 0xa438, 0x1352 }, { 0xa436, 0xa10a }, + { 0xa438, 0x0545 }, { 0xa436, 0xa108 }, { 0xa438, 0x01ed }, + { 0xa436, 0xa106 }, { 0xa438, 0x1bbf }, { 0xa436, 0xa104 }, + { 0xa438, 0x114b }, { 0xa436, 0xa102 }, { 0xa438, 0x14bf }, + { 0xa436, 0xa100 }, { 0xa438, 0x07ce }, { 0xa436, 0xa110 }, + { 0xa438, 0x00ff }, { 0xa436, 0xa016 }, { 0xa438, 0x0020 }, + { 0xa436, 0xa012 }, { 0xa438, 0x1ff8 }, { 0xa436, 0xa014 }, + { 0xa438, 0xd1ce }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, + { 0xa438, 0x0000 }, { 0xa438, 0x0000 }, { 0xa436, 0xa164 }, + { 0xa438, 0x07fc }, { 0xa436, 0xa166 }, { 0xa438, 0x143d }, + { 0xa436, 0xa168 }, { 0xa438, 0x3fff }, { 0xa436, 0xa16a }, + { 0xa438, 0x3fff }, { 0xa436, 0xa16c }, { 0xa438, 0x3fff }, + { 0xa436, 0xa16e }, { 0xa438, 0x3fff }, { 0xa436, 0xa170 }, + { 0xa438, 0x3fff }, { 0xa436, 0xa172 }, { 0xa438, 0x3fff }, + { 0xa436, 0xa162 }, { 0xa438, 0x0003 }, { 0xa436, 0xb87c }, + { 0xa438, 0x8994 }, { 0xa436, 0xb87e }, { 0xa438, 0xaf89 }, + { 0xa438, 0xacaf }, { 0xa438, 0x89e4 }, { 0xa438, 0xaf89 }, + { 0xa438, 0xecaf }, { 0xa438, 0x8a04 }, { 0xa438, 0xaf8a }, + { 0xa438, 0x2eaf }, { 0xa438, 0x8a4a }, { 0xa438, 0xaf8d }, + { 0xa438, 0x31af }, { 0xa438, 0x8dc6 }, { 0xa438, 0x1f55 }, + { 0xa438, 0xe18f }, { 0xa438, 0xe3a1 }, { 0xa438, 0x0007 }, + { 0xa438, 0xee86 }, { 0xa438, 0xe900 }, { 0xa438, 0xaf4f }, + { 0xa438, 0x9ead }, { 0xa438, 0x281b }, { 0xa438, 0xe18f }, + { 0xa438, 0xfcef }, { 0xa438, 0x71bf }, { 0xa438, 0x74f6 }, + { 0xa438, 0x027e }, { 0xa438, 0xd2ef }, { 0xa438, 0x641c }, + { 0xa438, 0x670d }, { 0xa438, 0x67ef }, { 0xa438, 0x461f }, + { 0xa438, 0x00bf }, { 0xa438, 0x74f6 }, { 0xa438, 0x027e }, + { 0xa438, 0xdee1 }, { 0xa438, 0x8fe3 }, { 0xa438, 0x0d11 }, + { 0xa438, 0xe58f }, { 0xa438, 0xe313 }, { 0xa438, 0xaeca }, + { 0xa438, 0x028d }, { 0xa438, 0xd1d3 }, { 0xa438, 0x01af }, + { 0xa438, 0x40d1 }, { 0xa438, 0xbf7a }, { 0xa438, 0x6102 }, + { 0xa438, 0x7d44 }, { 0xa438, 0xa100 }, { 0xa438, 0x09e0 }, + { 0xa438, 0x8ffa }, { 0xa438, 0xe18f }, { 0xa438, 0xfbaf }, + { 0xa438, 0x683d }, { 0xa438, 0x027f }, { 0xa438, 0xa9af }, + { 0xa438, 0x682c }, { 0xa438, 0xbf8e }, { 0xa438, 0x4102 }, + { 0xa438, 0x7d44 }, { 0xa438, 0xe58f }, { 0xa438, 0xecbf }, + { 0xa438, 0x74cc }, { 0xa438, 0x027d }, { 0xa438, 0x44e3 }, + { 0xa438, 0x8fed }, { 0xa438, 0x0d31 }, { 0xa438, 0xf63f }, + { 0xa438, 0x0d11 }, { 0xa438, 0xf62f }, { 0xa438, 0x1b13 }, + { 0xa438, 0xad2f }, { 0xa438, 0x06bf }, { 0xa438, 0x8e41 }, + { 0xa438, 0x027c }, { 0xa438, 0xf9d1 }, { 0xa438, 0x01af }, + { 0xa438, 0x5974 }, { 0xa438, 0xee88 }, { 0xa438, 0x8600 }, + { 0xa438, 0xe08f }, { 0xa438, 0xebad }, { 0xa438, 0x200b }, + { 0xa438, 0xe18f }, { 0xa438, 0xecbf }, { 0xa438, 0x8e41 }, + { 0xa438, 0x027d }, { 0xa438, 0x25ae }, { 0xa438, 0x04ee }, + { 0xa438, 0x8feb }, { 0xa438, 0x01af }, { 0xa438, 0x5945 }, + { 0xa438, 0xad28 }, { 0xa438, 0x2ce0 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}, { 0xa438, 0x766b }, { 0xa438, 0xfdef }, + { 0xa438, 0x95fd }, { 0xa438, 0xfc04 }, { 0xa438, 0xbf6e }, + { 0xa438, 0x0602 }, { 0xa438, 0x76b6 }, { 0xa438, 0xef64 }, + { 0xa438, 0xbf6e }, { 0xa438, 0x0902 }, { 0xa438, 0x76b6 }, + { 0xa438, 0x1e64 }, { 0xa438, 0xbf6e }, { 0xa438, 0x0f02 }, + { 0xa438, 0x76b6 }, { 0xa438, 0x1e64 }, { 0xa438, 0xac40 }, + { 0xa438, 0x0ebf }, { 0xa438, 0x7298 }, { 0xa438, 0x0276 }, + { 0xa438, 0xb6e5 }, { 0xa438, 0x8478 }, { 0xa438, 0xa10f }, + { 0xa438, 0x26ae }, { 0xa438, 0x47bf }, { 0xa438, 0x8bf3 }, + { 0xa438, 0x0276 }, { 0xa438, 0xb6ac }, { 0xa438, 0x2802 }, + { 0xa438, 0xae0b }, { 0xa438, 0xbf8b }, { 0xa438, 0xf902 }, + { 0xa438, 0x76b6 }, { 0xa438, 0xe584 }, { 0xa438, 0x78ae }, + { 0xa438, 0x09bf }, { 0xa438, 0x8bf6 }, { 0xa438, 0x0276 }, + { 0xa438, 0xb6e5 }, { 0xa438, 0x8478 }, { 0xa438, 0xa103 }, + { 0xa438, 0x02ae }, { 0xa438, 0x23e0 }, { 0xa438, 0x8474 }, + { 0xa438, 0xe184 }, { 0xa438, 0x75ef }, { 0xa438, 0x64e0 }, + { 0xa438, 0x83fc }, { 0xa438, 0xe183 }, { 0xa438, 0xfdef }, + { 0xa438, 0x7402 }, { 0xa438, 0x75d9 }, { 0xa438, 0xad50 }, + { 0xa438, 0x0ae0 }, { 0xa438, 0x83ec }, { 0xa438, 0xf721 }, + { 0xa438, 0xe483 }, { 0xa438, 0xecae }, { 0xa438, 0x03af }, + { 0xa438, 0x68e4 }, { 0xa438, 0xbf72 }, { 0xa438, 0x9502 }, + { 0xa438, 0x766b }, { 0xa438, 0xe083 }, { 0xa438, 0xebad }, + { 0xa438, 0x2170 }, { 0xa438, 0xbf73 }, { 0xa438, 0x7f02 }, + { 0xa438, 0x766b }, { 0xa438, 0xd700 }, { 0xa438, 0x64bf }, + { 0xa438, 0x73c4 }, { 0xa438, 0x0276 }, { 0xa438, 0xb6a4 }, + { 0xa438, 0x0000 }, { 0xa438, 0x02ae }, { 0xa438, 0x0d87 }, + { 0xa438, 0xa700 }, { 0xa438, 0x00ef }, { 0xa438, 0xe183 }, + { 0xa438, 0xecf7 }, { 0xa438, 0x2ae5 }, { 0xa438, 0x83ec }, + { 0xa438, 0xbf73 }, { 0xa438, 0xbe02 }, { 0xa438, 0x766b }, + { 0xa438, 0xbf73 }, { 0xa438, 0xb802 }, { 0xa438, 0x766b }, + { 0xa438, 0xbf73 }, { 0xa438, 0xc102 }, { 0xa438, 0x766b }, + { 0xa438, 0xbf73 }, { 0xa438, 0xbb02 }, { 0xa438, 0x766b }, + { 0xa438, 0xe084 }, { 0xa438, 0x9ee1 }, { 0xa438, 0x849f }, + { 0xa438, 0xbf72 }, { 0xa438, 0x7d02 }, { 0xa438, 0x7697 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8002 }, { 0xa438, 0x7697 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8302 }, { 0xa438, 0x7697 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8602 }, { 0xa438, 0x7697 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8902 }, { 0xa438, 0x7674 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8c02 }, { 0xa438, 0x7674 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x8f02 }, { 0xa438, 0x7674 }, + { 0xa438, 0xbf72 }, { 0xa438, 0x9202 }, { 0xa438, 0x7674 }, + { 0xa438, 0xee84 }, { 0xa438, 0x7700 }, { 0xa438, 0xe080 }, + { 0xa438, 0x44f6 }, { 0xa438, 0x21e4 }, { 0xa438, 0x8044 }, + { 0xa438, 0xaf68 }, { 0xa438, 0xe411 }, { 0xa438, 0xd1a4 }, + { 0xa438, 0x10bc }, { 0xa438, 0x7432 }, { 0xa438, 0xbc74 }, + { 0xa438, 0xbbbf }, { 0xa438, 0x14cc }, { 0xa438, 0xbfaa }, + { 0xa438, 0x00bf }, { 0xa438, 0x9055 }, { 0xa438, 0xbf06 }, + { 0xa438, 0x10bf }, { 0xa438, 0xb876 }, { 0xa438, 0xbe02 }, + { 0xa438, 0x54be }, { 0xa438, 0x0232 }, { 0xa438, 0xbe02 }, + { 0xa438, 0x10be }, { 0xa438, 0x0200 }, { 0xa436, 0x8fe7 }, + { 0xa438, 0x1200 }, { 0xa436, 0x8fe9 }, { 0xa438, 0x1200 }, + { 0xa436, 0x8feb }, { 0xa438, 0x1200 }, { 0xa436, 0x8fed }, + { 0xa438, 0x1200 }, { 0xa436, 0x8fef }, { 0xa438, 0x1200 }, + { 0xa436, 0x8ff1 }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff3 }, + { 0xa438, 0x1200 }, { 0xa436, 0x8ff5 }, { 0xa438, 0x1200 }, + { 0xa436, 0x8ff7 }, { 0xa438, 0x1200 }, { 0xa436, 0x8ff9 }, + { 0xa438, 0x1200 }, { 0xa436, 0x8ffb }, { 0xa438, 0x1200 }, + { 0xa436, 0x8ffd }, { 0xa438, 0x1200 }, { 0xa436, 0xb818 }, + { 0xa438, 0x6602 }, { 0xa436, 0xb81a }, { 0xa438, 0x1f75 }, + { 0xa436, 0xb81c }, { 0xa438, 0x67eb }, { 0xa436, 0xb81e }, + { 0xa438, 0xffff }, { 0xa436, 0xb850 }, { 0xa438, 0xffff }, + { 0xa436, 0xb852 }, { 0xa438, 0xffff }, { 0xa436, 0xb878 }, + { 0xa438, 0xffff }, { 0xa436, 0xb884 }, { 0xa438, 0xffff }, + { 0xa436, 0xb832 }, { 0xa438, 0x0007 }, { 0xb82e, 0x0000 }, + { 0xa436, 0x8023 }, { 0xa438, 0x0000 }, { 0xb820, 0x0000 }, + { 0xb892, 0x0000 }, { 0xb88e, 0xc07c }, { 0xb890, 0x0203 }, + { 0xb890, 0x0304 }, { 0xb890, 0x0405 }, { 0xb890, 0x0607 }, + { 0xb890, 0x0809 }, { 0xb890, 0x0b0d }, { 0xb890, 0x0f11 }, + { 0xb890, 0x1418 }, { 0xb890, 0x1b20 }, { 0xb890, 0x252b }, + { 0xb890, 0x343e }, { 0xb890, 0x4854 }, { 0xb890, 0x6203 }, + { 0xb890, 0x0304 }, { 0xb890, 0x0506 }, { 0xb890, 0x080a }, + { 0xb890, 0x0c0e }, { 0xb890, 0x1216 }, { 0xb890, 0x1b22 }, + { 0xb890, 0x2a34 }, { 0xb890, 0x404f }, { 0xb890, 0x6171 }, + { 0xb890, 0x7884 }, { 0xb890, 0x9097 }, { 0xb890, 0x0203 }, + { 0xb890, 0x0406 }, { 0xb890, 0x080b }, { 0xb890, 0x0e13 }, + { 0xb890, 0x1820 }, { 0xb890, 0x2a39 }, { 0xb890, 0x4856 }, + { 0xb890, 0xe060 }, { 0xb890, 0xe050 }, { 0xb890, 0xd080 }, + { 0xb890, 0x8070 }, { 0xb890, 0x70a0 }, { 0xb890, 0x1000 }, + { 0xb890, 0x60d0 }, { 0xb890, 0xb010 }, { 0xb890, 0xe0b0 }, + { 0xb890, 0x80c0 }, { 0xb890, 0xe000 }, { 0xb890, 0x2020 }, + { 0xb890, 0x1020 }, { 0xb890, 0xe090 }, { 0xb890, 0x80c0 }, + { 0xb890, 0x3020 }, { 0xb890, 0x00e0 }, { 0xb890, 0x40a0 }, + { 0xb890, 0xe020 }, { 0xb890, 0x5060 }, { 0xb890, 0xe0d0 }, + { 0xb890, 0xa000 }, { 0xb890, 0x3030 }, { 0xb890, 0x4070 }, + { 0xb890, 0xe0e0 }, { 0xb890, 0xd080 }, { 0xb890, 0xa010 }, + { 0xb890, 0xe040 }, { 0xb890, 0x80b0 }, { 0xb890, 0x50b0 }, + { 0xb890, 0x2090 }, { 0xb820, 0x0000 } +}; + +/* + * These should just be arrays as well, but to make diffing with + * OpenBSD easier I'm going to leave them as-is until kevlo@ wants + * to sync them! + */ + +#define MAC_R25_MCU \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x808f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8093 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8097 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x809d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80a1 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80aa }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x607b }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0xf00e }, \ + { 0xa438, 0x42da }, \ + { 0xa438, 0xf01e }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x615b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf01c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf024 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf02c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14a4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14bc }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5f2e }, \ + { 0xa438, 0xf034 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac11 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa410 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4779 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf034 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac22 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa420 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4559 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf023 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac44 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa440 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4339 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf012 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4118 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac88 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa480 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x4119 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xac0f }, \ + { 0xa438, 0xae01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1444 }, \ + { 0xa438, 0xf001 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1456 }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5fac }, \ + { 0xa438, 0xc48f }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x141b }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x121a }, \ + { 0xa438, 0xd0b4 }, \ + { 0xa438, 0xd1bb }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0898 }, \ + { 0xa438, 0xd0b4 }, \ + { 0xa438, 0xd1bb }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a0e }, \ + { 0xa438, 0xd064 }, \ + { 0xa438, 0xd18a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0b7e }, \ + { 0xa438, 0x401c }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xa804 }, \ + { 0xa438, 0x8804 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x053b }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0648 }, \ + { 0xa438, 0xc520 }, \ + { 0xa438, 0xa201 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x252d }, \ + { 0xa438, 0x1646 }, \ + { 0xa438, 0xd708 }, \ + { 0xa438, 0x4006 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1646 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0308 }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0x0307 }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0x1645 }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x0647 }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x053a }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x0b7c }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x0a0c }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x0896 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x11a1 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0xff00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8015 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0xad02 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x02d7 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00ed }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0509 }, \ + { 0xa438, 0xc100 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x008f }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x008d }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x00eb }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x0103 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8018 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8024 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8055 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8072 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80dc }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xfffd }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xfffd }, \ + { 0xa438, 0x8301 }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0xa70c }, \ + { 0xa438, 0x9402 }, \ + { 0xa438, 0x890c }, \ + { 0xa438, 0x8840 }, \ + { 0xa438, 0xa380 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xcb91 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd139 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd140 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xb404 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e0 }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xa110 }, \ + { 0xa438, 0xa2a0 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4085 }, \ + { 0xa438, 0xa180 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x8280 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07f0 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5f74 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb6 }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x82a0 }, \ + { 0xa438, 0x8404 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0d01 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e0 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xd158 }, \ + { 0xa438, 0xd04d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x03d4 }, \ + { 0xa438, 0x94bc }, \ + { 0xa438, 0x870c }, \ + { 0xa438, 0x8380 }, \ + { 0xa438, 0xd10d }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07c4 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xa190 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa280 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0xa220 }, \ + { 0xa438, 0xd130 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07c4 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xbb80 }, \ + { 0xa438, 0xd1c4 }, \ + { 0xa438, 0xd074 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x604b }, \ + { 0xa438, 0xa90c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0556 }, \ + { 0xa438, 0xcb92 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x4063 }, \ + { 0xa438, 0xd116 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd119 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x60a0 }, \ + { 0xa438, 0x6241 }, \ + { 0xa438, 0x63e2 }, \ + { 0xa438, 0x6583 }, \ + { 0xa438, 0xf054 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d10 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf02f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d50 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf02a }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d20 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf021 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d60 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf01c }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d30 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf013 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d70 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0xf00e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x611e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x40da }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d40 }, \ + { 0xa438, 0xa010 }, \ + { 0xa438, 0x8740 }, \ + { 0xa438, 0xf005 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d80 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e8 }, \ + { 0xa438, 0xa610 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x405d }, \ + { 0xa438, 0xa720 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5ff4 }, \ + { 0xa438, 0xa008 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x4046 }, \ + { 0xa438, 0xa002 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07fb }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x7f6f }, \ + { 0xa438, 0x7f4e }, \ + { 0xa438, 0x7f2d }, \ + { 0xa438, 0x7f0c }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0d00 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x07e8 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0xa740 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0743 }, \ + { 0xa438, 0xd702 }, \ + { 0xa438, 0x7fb5 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x3ad4 }, \ + { 0xa438, 0x0556 }, \ + { 0xa438, 0x8610 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x066e }, \ + { 0xa438, 0xd1f5 }, \ + { 0xa438, 0xd049 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x01ec }, \ + { 0xa436, 0xa10e }, \ + { 0xa438, 0x01ea }, \ + { 0xa436, 0xa10c }, \ + { 0xa438, 0x06a9 }, \ + { 0xa436, 0xa10a }, \ + { 0xa438, 0x078a }, \ + { 0xa436, 0xa108 }, \ + { 0xa438, 0x03d2 }, \ + { 0xa436, 0xa106 }, \ + { 0xa438, 0x067f }, \ + { 0xa436, 0xa104 }, \ + { 0xa438, 0x0665 }, \ + { 0xa436, 0xa102 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa100 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa110 }, \ + { 0xa438, 0x00fc }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8530 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x3caf }, \ + { 0xa438, 0x8545 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0x45af }, \ + { 0xa438, 0x8545 }, \ + { 0xa438, 0xee82 }, \ + { 0xa438, 0xf900 }, \ + { 0xa438, 0x0103 }, \ + { 0xa438, 0xaf03 }, \ + { 0xa438, 0xb7f8 }, \ + { 0xa438, 0xe0a6 }, \ + { 0xa438, 0x00e1 }, \ + { 0xa438, 0xa601 }, \ + { 0xa438, 0xef01 }, \ + { 0xa438, 0x58f0 }, \ + { 0xa438, 0xa080 }, \ + { 0xa438, 0x37a1 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0xae16 }, \ + { 0xa438, 0xa185 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x11a1 }, \ + { 0xa438, 0x8702 }, \ + { 0xa438, 0xae0c }, \ + { 0xa438, 0xa188 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x07a1 }, \ + { 0xa438, 0x8902 }, \ + { 0xa438, 0xae02 }, \ + { 0xa438, 0xae1c }, \ + { 0xa438, 0xe0b4 }, \ + { 0xa438, 0x62e1 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0x6901 }, \ + { 0xa438, 0xe4b4 }, \ + { 0xa438, 0x62e5 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0xe0b4 }, \ + { 0xa438, 0x62e1 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0x6901 }, \ + { 0xa438, 0xe4b4 }, \ + { 0xa438, 0x62e5 }, \ + { 0xa438, 0xb463 }, \ + { 0xa438, 0xfc04 }, \ + { 0xa436, 0xb85e }, \ + { 0xa438, 0x03b3 }, \ + { 0xa436, 0xb860 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb862 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb864 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0x0001 } + +#define MAC_R25B_MCU \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x3701 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0001 }, \ + { 0xb820, 0x0090 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803f }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8045 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8067 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x806d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8071 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80b1 }, \ + { 0xa438, 0xd093 }, \ + { 0xa438, 0xd1c4 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x5fbc }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9f1 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0fc9 }, \ + { 0xa438, 0xbb50 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0xa202 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x8c0f }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1519 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x5fae }, \ + { 0xa438, 0x9b50 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x7fae }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x40a7 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x4071 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1557 }, \ + { 0xa438, 0xd719 }, \ + { 0xa438, 0x2f70 }, \ + { 0xa438, 0x803b }, \ + { 0xa438, 0x2f73 }, \ + { 0xa438, 0x156a }, \ + { 0xa438, 0x5e70 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x155d }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0xa202 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xffed }, \ + { 0xa438, 0xd709 }, \ + { 0xa438, 0x4054 }, \ + { 0xa438, 0xa788 }, \ + { 0xa438, 0xd70b }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x172a }, \ + { 0xa438, 0xc0c1 }, \ + { 0xa438, 0xc0c0 }, \ + { 0xa438, 0xd05a }, \ + { 0xa438, 0xd1ba }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x2529 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0xd0a7 }, \ + { 0xa438, 0xd1b9 }, \ + { 0xa438, 0xa208 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x080e }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x408b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a65 }, \ + { 0xa438, 0xf003 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0a6b }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0915 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0909 }, \ + { 0xa438, 0x228f }, \ + { 0xa438, 0x804e }, \ + { 0xa438, 0x9801 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x5d61 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0x2005 }, \ + { 0xa438, 0x091a }, \ + { 0xa438, 0x3bd9 }, \ + { 0xa438, 0x0919 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0916 }, \ + { 0xa438, 0xd090 }, \ + { 0xa438, 0xd1c9 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1064 }, \ + { 0xa438, 0xd096 }, \ + { 0xa438, 0xd1a9 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0xa104 }, \ + { 0xa438, 0x0c07 }, \ + { 0xa438, 0x0902 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xbc10 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0xa201 }, \ + { 0xa438, 0x8201 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xc484 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0xcc02 }, \ + { 0xa438, 0xcd0d }, \ + { 0xa438, 0xaf01 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x4371 }, \ + { 0xa438, 0xbd08 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x5fb3 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0xd0f5 }, \ + { 0xa438, 0xd1c6 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0e50 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x401c }, \ + { 0xa438, 0xd0f5 }, \ + { 0xa438, 0xd1c6 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0ea0 }, \ + { 0xa438, 0x401c }, \ + { 0xa438, 0xd07b }, \ + { 0xa438, 0xd1c5 }, \ + { 0xa438, 0x8ef0 }, \ + { 0xa438, 0x401c }, \ + { 0xa438, 0x9d08 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x7fb3 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x5fad }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x14c5 }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x3181 }, \ + { 0xa438, 0x80af }, \ + { 0xa438, 0x60ad }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x135c }, \ + { 0xa438, 0xd703 }, \ + { 0xa438, 0x5fba }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0cc7 }, \ + { 0xa438, 0xa802 }, \ + { 0xa438, 0xa301 }, \ + { 0xa438, 0xa801 }, \ + { 0xa438, 0xc004 }, \ + { 0xa438, 0xd710 }, \ + { 0xa438, 0x4000 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1e79 }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0x1e78 }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0x0c93 }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x1062 }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x0915 }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x020a }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x1726 }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x1542 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x0fc7 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0xff00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801d }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802c }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6090 }, \ + { 0xa438, 0x60d1 }, \ + { 0xa438, 0xc95c }, \ + { 0xa438, 0xf007 }, \ + { 0xa438, 0x60b1 }, \ + { 0xa438, 0xc95a }, \ + { 0xa438, 0xf004 }, \ + { 0xa438, 0xc956 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xc94e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00cd }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6090 }, \ + { 0xa438, 0x60d1 }, \ + { 0xa438, 0xc95c }, \ + { 0xa438, 0xf007 }, \ + { 0xa438, 0x60b1 }, \ + { 0xa438, 0xc95a }, \ + { 0xa438, 0xf004 }, \ + { 0xa438, 0xc956 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xc94e }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x022a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0132 }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x012f }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x00cc }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x0103 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8020 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x802a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8035 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0xd107 }, \ + { 0xa438, 0xd042 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x8280 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6065 }, \ + { 0xa438, 0xd125 }, \ + { 0xa438, 0xf002 }, \ + { 0xa438, 0xd12b }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x077f }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c50 }, \ + { 0xa438, 0xd104 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0aa8 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0a2e }, \ + { 0xa438, 0xcb9b }, \ + { 0xa438, 0xd110 }, \ + { 0xa438, 0xd040 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x0b7b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x081b }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x09df }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x7fb8 }, \ + { 0xa438, 0xa718 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x074e }, \ + { 0xa436, 0xa10e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa10c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa10a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa108 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa106 }, \ + { 0xa438, 0x074d }, \ + { 0xa436, 0xa104 }, \ + { 0xa438, 0x0818 }, \ + { 0xa436, 0xa102 }, \ + { 0xa438, 0x0a2c }, \ + { 0xa436, 0xa100 }, \ + { 0xa438, 0x077e }, \ + { 0xa436, 0xa110 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xb87c }, \ + { 0xa438, 0x8625 }, \ + { 0xa436, 0xb87e }, \ + { 0xa438, 0xaf86 }, \ + { 0xa438, 0x3daf }, \ + { 0xa438, 0x8689 }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x69af }, \ + { 0xa438, 0x8887 }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0x9caf }, \ + { 0xa438, 0x88be }, \ + { 0xa438, 0xaf88 }, \ + { 0xa438, 0xbeaf }, \ + { 0xa438, 0x88be }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0x49d7 }, \ + { 0xa438, 0x0040 }, \ + { 0xa438, 0x0277 }, \ + { 0xa438, 0x7daf }, \ + { 0xa438, 0x2727 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7205 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7208 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x71f3 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x71f6 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7229 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x722c }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7217 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x721a }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x721d }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7211 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7220 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7214 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x722f }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7223 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7232 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0x7226 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfae0 }, \ + { 0xa438, 0x85b3 }, \ + { 0xa438, 0x3802 }, \ + { 0xa438, 0xad27 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x8830 }, \ + { 0xa438, 0x1f66 }, \ + { 0xa438, 0xef65 }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x1f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00da }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x2f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00db }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4202 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1b03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4502 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xef02 }, \ + { 0xa438, 0x1a03 }, \ + { 0xa438, 0x1f11 }, \ + { 0xa438, 0x0d42 }, \ + { 0xa438, 0xbf88 }, \ + { 0xa438, 0x4802 }, \ + { 0xa438, 0x6e7d }, \ + { 0xa438, 0xbfc2 }, \ + { 0xa438, 0x3f1a }, \ + { 0xa438, 0x96f7 }, \ + { 0xa438, 0x05ee }, \ + { 0xa438, 0xffd2 }, \ + { 0xa438, 0x00da }, \ + { 0xa438, 0xf605 }, \ + { 0xa438, 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}, \ + { 0xa438, 0x547b }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ff8 }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xf9bf }, \ + { 0xa438, 0x547e }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffa }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x5481 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffc }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xfdbf }, \ + { 0xa438, 0x5484 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8e4 }, \ + { 0xa438, 0x8ffe }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xffbf }, \ + { 0xa438, 0x5322 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x4448 }, \ + { 0xa438, 0xaf85 }, \ + { 0xa438, 0xa7bf }, \ + { 0xa438, 0x5322 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x313c }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x7b02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xf8e5 }, \ + { 0xa438, 0x8ff9 }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x7e02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfae5 }, \ + { 0xa438, 0x8ffb }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x8102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfce5 }, \ + { 0xa438, 0x8ffd }, \ + { 0xa438, 0xbf54 }, \ + { 0xa438, 0x8402 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0xfee5 }, \ + { 0xa438, 0x8fff }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xa131 }, \ + { 0xa438, 0x03af }, \ + { 0xa438, 0x85a7 }, \ + { 0xa438, 0xd480 }, \ + { 0xa438, 0x00bf }, \ + { 0xa438, 0x8684 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x8687 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868a }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9bf }, \ + { 0xa438, 0x868d }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xa9ef }, \ + { 0xa438, 0x95fd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf0d1 }, \ + { 0xa438, 0x2af0 }, \ + { 0xa438, 0xd12c }, \ + { 0xa438, 0xf0d1 }, \ + { 0xa438, 0x44f0 }, \ + { 0xa438, 0xd146 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xa102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xbf86 }, \ + { 0xa438, 0xa102 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xd101 }, \ + { 0xa438, 0xaf06 }, \ + { 0xa438, 0xa570 }, \ + { 0xa438, 0xce42 }, \ + { 0xa438, 0xee83 }, \ + { 0xa438, 0xc800 }, \ + { 0xa438, 0x0286 }, \ + { 0xa438, 0xba02 }, \ + { 0xa438, 0x8728 }, \ + { 0xa438, 0x0287 }, \ + { 0xa438, 0xbe02 }, \ + { 0xa438, 0x87f9 }, \ + { 0xa438, 0x0288 }, \ + { 0xa438, 0xc3af }, \ + { 0xa438, 0x4771 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfafb }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xfae0 }, \ + { 0xa438, 0x8015 }, \ + { 0xa438, 0xad25 }, \ + { 0xa438, 0x45d2 }, \ + { 0xa438, 0x0002 }, \ + { 0xa438, 0x8714 }, \ + { 0xa438, 0xac4f }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x0bef }, \ + { 0xa438, 0x46f6 }, \ + { 0xa438, 0x273c }, \ + { 0xa438, 0x0400 }, \ + { 0xa438, 0xab26 }, \ + { 0xa438, 0xae30 }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xe9e1 }, \ + { 0xa438, 0x8fea }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xab26 }, \ + { 0xa438, 0xef32 }, \ + { 0xa438, 0x0c31 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0xe91a }, \ + { 0xa438, 0x93d8 }, \ + { 0xa438, 0x19d9 }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xab0a }, \ + { 0xa438, 0x19d8 }, \ + { 0xa438, 0x19d9 }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xaa02 }, \ + { 0xa438, 0xae0c }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1202 }, \ + { 0xa438, 0x58b1 }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1202 }, \ + { 0xa438, 0x58a8 }, \ + { 0xa438, 0xfeef }, \ + { 0xa438, 0x96ff }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fb }, \ + { 0xa438, 0xef79 }, \ + { 0xa438, 0xa200 }, \ + { 0xa438, 0x08bf }, \ + { 0xa438, 0x892e }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ef }, \ + { 0xa438, 0x64ef }, \ + { 0xa438, 0x97ff }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfafb }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xfae0 }, \ + { 0xa438, 0x8015 }, \ + { 0xa438, 0xad25 }, \ + { 0xa438, 0x50d2 }, \ + { 0xa438, 0x0002 }, \ + { 0xa438, 0x878d }, \ + { 0xa438, 0xac4f }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x0bef }, \ + { 0xa438, 0x46f6 }, \ + { 0xa438, 0x273c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0xab31 }, \ + { 0xa438, 0xae29 }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xede1 }, \ + { 0xa438, 0x8fee }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xab1f }, \ + { 0xa438, 0xa200 }, \ + { 0xa438, 0x04ef }, \ + { 0xa438, 0x32ae }, \ + { 0xa438, 0x02d3 }, \ + { 0xa438, 0x010c }, \ + { 0xa438, 0x31bf }, \ + { 0xa438, 0x8fed }, \ + { 0xa438, 0x1a93 }, \ + { 0xa438, 0xd819 }, \ + { 0xa438, 0xd91b }, \ + { 0xa438, 0x46ab }, \ + { 0xa438, 0x0e19 }, \ + { 0xa438, 0xd819 }, \ + { 0xa438, 0xd91b }, \ + { 0xa438, 0x46aa }, \ + { 0xa438, 0x0612 }, \ + { 0xa438, 0xa205 }, \ + { 0xa438, 0xc0ae }, \ + { 0xa438, 0x0cbf }, \ + { 0xa438, 0x5712 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xb1bf }, \ + { 0xa438, 0x5712 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xa8fe }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xfdfc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x79a2 }, \ + { 0xa438, 0x0005 }, \ + { 0xa438, 0xbf89 }, \ + { 0xa438, 0x1fae }, \ + { 0xa438, 0x1ba2 }, \ + { 0xa438, 0x0105 }, \ + { 0xa438, 0xbf89 }, \ + { 0xa438, 0x22ae }, \ + { 0xa438, 0x13a2 }, \ + { 0xa438, 0x0205 }, \ + { 0xa438, 0xbf89 }, \ + { 0xa438, 0x25ae }, \ + { 0xa438, 0x0ba2 }, \ + { 0xa438, 0x0305 }, \ + { 0xa438, 0xbf89 }, \ + { 0xa438, 0x28ae }, \ + { 0xa438, 0x03bf }, \ + { 0xa438, 0x892b }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ef }, \ + { 0xa438, 0x64ef }, \ + { 0xa438, 0x97ff }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfaef }, \ + { 0xa438, 0x69fa }, \ + { 0xa438, 0xe080 }, \ + { 0xa438, 0x15ad }, \ + { 0xa438, 0x2628 }, \ + { 0xa438, 0xe081 }, \ + { 0xa438, 0xabe1 }, \ + { 0xa438, 0x81ac }, \ + { 0xa438, 0xef64 }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1802 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xaa0a }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1b02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xab0c }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x58b1 }, \ + { 0xa438, 0xbf57 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x58a8 }, \ + { 0xa438, 0xfeef }, \ + { 0xa438, 0x96fe }, \ + { 0xa438, 0xfdfc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xf9ef }, \ + { 0xa438, 0x59f9 }, \ + { 0xa438, 0xe080 }, \ + { 0xa438, 0x15ad }, \ + { 0xa438, 0x2622 }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x2202 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0x3972 }, \ + { 0xa438, 0x9e10 }, \ + { 0xa438, 0xe083 }, \ + { 0xa438, 0xc9ac }, \ + { 0xa438, 0x2605 }, \ + { 0xa438, 0x0288 }, \ + { 0xa438, 0x2cae }, \ + { 0xa438, 0x0d02 }, \ + { 0xa438, 0x8870 }, \ + { 0xa438, 0xae08 }, \ + { 0xa438, 0xe283 }, \ + { 0xa438, 0xc9f6 }, \ + { 0xa438, 0x36e6 }, \ + { 0xa438, 0x83c9 }, \ + { 0xa438, 0xfdef }, \ + { 0xa438, 0x95fd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfafb }, \ + { 0xa438, 0xef79 }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x5718 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ef }, \ + { 0xa438, 0x64e2 }, \ + { 0xa438, 0x8fe5 }, \ + { 0xa438, 0xe38f }, \ + { 0xa438, 0xe61b }, \ + { 0xa438, 0x659e }, \ + { 0xa438, 0x10e4 }, \ + { 0xa438, 0x8fe5 }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xe6e2 }, \ + { 0xa438, 0x83c9 }, \ + { 0xa438, 0xf636 }, \ + { 0xa438, 0xe683 }, \ + { 0xa438, 0xc9ae }, \ + { 0xa438, 0x13e2 }, \ + { 0xa438, 0x83c9 }, \ + { 0xa438, 0xf736 }, \ + { 0xa438, 0xe683 }, \ + { 0xa438, 0xc902 }, \ + { 0xa438, 0x5820 }, \ + { 0xa438, 0xef57 }, \ + { 0xa438, 0xe68f }, \ + { 0xa438, 0xe7e7 }, \ + { 0xa438, 0x8fe8 }, \ + { 0xa438, 0xffef }, \ + { 0xa438, 0x97ff }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfafb }, \ + { 0xa438, 0xef79 }, \ + { 0xa438, 0xfbe2 }, \ + { 0xa438, 0x8fe7 }, \ + { 0xa438, 0xe38f }, \ + { 0xa438, 0xe8ef }, \ + { 0xa438, 0x65e2 }, \ + { 0xa438, 0x81b8 }, \ + { 0xa438, 0xe381 }, \ + { 0xa438, 0xb9ef }, \ + { 0xa438, 0x7502 }, \ + { 0xa438, 0x583b }, \ + { 0xa438, 0xac50 }, \ + { 0xa438, 0x1abf }, \ + { 0xa438, 0x5718 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ef }, \ + { 0xa438, 0x64e2 }, \ + { 0xa438, 0x8fe5 }, \ + { 0xa438, 0xe38f }, \ + { 0xa438, 0xe61b }, \ + { 0xa438, 0x659e }, \ + { 0xa438, 0x1ce4 }, \ + { 0xa438, 0x8fe5 }, \ + { 0xa438, 0xe58f }, \ + { 0xa438, 0xe6ae }, \ + { 0xa438, 0x0cbf }, \ + { 0xa438, 0x5715 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xb1bf }, \ + { 0xa438, 0x5715 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xa8e2 }, \ + { 0xa438, 0x83c9 }, \ + { 0xa438, 0xf636 }, \ + { 0xa438, 0xe683 }, \ + { 0xa438, 0xc9ff }, \ + { 0xa438, 0xef97 }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xfdfc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xf9fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xe080 }, \ + { 0xa438, 0x15ad }, \ + { 0xa438, 0x264b }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0xca02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xad28 }, \ + { 0xa438, 0x42bf }, \ + { 0xa438, 0x8931 }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8ef }, \ + { 0xa438, 0x54bf }, \ + { 0xa438, 0x576c }, \ + { 0xa438, 0x0252 }, \ + { 0xa438, 0xc8a1 }, \ + { 0xa438, 0x001b }, \ + { 0xa438, 0xbf53 }, \ + { 0xa438, 0x4c02 }, \ + { 0xa438, 0x52c8 }, \ + { 0xa438, 0xac29 }, \ + { 0xa438, 0x0dac }, \ + { 0xa438, 0x2805 }, \ + { 0xa438, 0xa302 }, \ + { 0xa438, 0x16ae }, \ + { 0xa438, 0x20a3 }, \ + { 0xa438, 0x0311 }, \ + { 0xa438, 0xae1b }, \ + { 0xa438, 0xa304 }, \ + { 0xa438, 0x0cae }, \ + { 0xa438, 0x16a3 }, \ + { 0xa438, 0x0802 }, \ + { 0xa438, 0xae11 }, \ + { 0xa438, 0xa309 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x0cbf }, \ + { 0xa438, 0x5715 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xb1bf }, \ + { 0xa438, 0x5715 }, \ + { 0xa438, 0x0258 }, \ + { 0xa438, 0xa8ef }, \ + { 0xa438, 0x96fe }, \ + { 0xa438, 0xfdfc }, \ + { 0xa438, 0x04f0 }, \ + { 0xa438, 0xa300 }, \ + { 0xa438, 0xf0a3 }, \ + { 0xa438, 0x02f0 }, \ + { 0xa438, 0xa304 }, \ + { 0xa438, 0xf0a3 }, \ + { 0xa438, 0x06f0 }, \ + { 0xa438, 0xa308 }, \ + { 0xa438, 0xf0a2 }, \ + { 0xa438, 0x8074 }, \ + { 0xa438, 0xa600 }, \ + { 0xa438, 0xac4f }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0x0bef }, \ + { 0xa438, 0x46f6 }, \ + { 0xa438, 0x273c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0xab1b }, \ + { 0xa438, 0xae16 }, \ + { 0xa438, 0xe081 }, \ + { 0xa438, 0xabe1 }, \ + { 0xa438, 0x81ac }, \ + { 0xa438, 0x1b46 }, \ + { 0xa438, 0xab0c }, \ + { 0xa438, 0xac32 }, \ + { 0xa438, 0x04ef }, \ + { 0xa438, 0x32ae }, \ + { 0xa438, 0x02d3 }, \ + { 0xa438, 0x04af }, \ + { 0xa438, 0x486c }, \ + { 0xa438, 0xaf48 }, \ + { 0xa438, 0x82af }, \ + { 0xa438, 0x4888 }, \ + { 0xa438, 0xe081 }, \ + { 0xa438, 0x9be1 }, \ + { 0xa438, 0x819c }, \ + { 0xa438, 0xe28f }, \ + { 0xa438, 0xe3ad }, \ + { 0xa438, 0x3009 }, \ + { 0xa438, 0x1f55 }, \ + { 0xa438, 0xe38f }, \ + { 0xa438, 0xe20c }, \ + { 0xa438, 0x581a }, \ + { 0xa438, 0x45e4 }, \ + { 0xa438, 0x83a6 }, \ + { 0xa438, 0xe583 }, \ + { 0xa438, 0xa7af }, \ + { 0xa438, 0x2a75 }, \ + { 0xa438, 0xe08f }, \ + { 0xa438, 0xe3ad }, \ + { 0xa438, 0x201c }, \ + { 0xa438, 0x1f44 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0xe10c }, \ + { 0xa438, 0x44ef }, \ + { 0xa438, 0x64e0 }, \ + { 0xa438, 0x8232 }, \ + { 0xa438, 0xe182 }, \ + { 0xa438, 0x331b }, \ + { 0xa438, 0x649f }, \ + { 0xa438, 0x091f }, \ + { 0xa438, 0x44e1 }, \ + { 0xa438, 0x8fe2 }, \ + { 0xa438, 0x0c48 }, \ + { 0xa438, 0x1b54 }, \ + { 0xa438, 0xe683 }, \ + { 0xa438, 0xa6e7 }, \ + { 0xa438, 0x83a7 }, \ + { 0xa438, 0xaf2b }, \ + { 0xa438, 0xd900 }, \ + { 0xa436, 0xb818 }, \ + { 0xa438, 0x043d }, \ + { 0xa436, 0xb81a }, \ + { 0xa438, 0x06a3 }, \ + { 0xa436, 0xb81c }, \ + { 0xa438, 0x476d }, \ + { 0xa436, 0xb81e }, \ + { 0xa438, 0x4852 }, \ + { 0xa436, 0xb850 }, \ + { 0xa438, 0x2a69 }, \ + { 0xa436, 0xb852 }, \ + { 0xa438, 0x2bd3 }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb884 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xb832 }, \ + { 0xa438, 0x003f }, \ + { 0xb844, 0xffff }, \ + { 0xa436, 0x8fe9 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x8feb }, \ + { 0xa438, 0x02fe }, \ + { 0xa436, 0x8fed }, \ + { 0xa438, 0x0019 }, \ + { 0xa436, 0x8fef }, \ + { 0xa438, 0x0bdb }, \ + { 0xa436, 0x8ff1 }, \ + { 0xa438, 0x0ca4 }, \ + { 0xa436, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x8024 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x801e }, \ + { 0xa438, 0x0024 }, \ + { 0xb820, 0x0000 } + +#define MAC_R25D_MCU \ + { 0xa436, 0x8023 }, \ + { 0xa438, 0x3800 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0001 }, \ + { 0xb820, 0x0090 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8018 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8021 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8029 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8031 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8035 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x819c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x81e9 }, \ + { 0xa438, 0xd711 }, \ + { 0xa438, 0x6081 }, \ + { 0xa438, 0x8904 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x2021 }, \ + { 0xa438, 0xa904 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x2021 }, \ + { 0xa438, 0xd75f }, \ + { 0xa438, 0x4083 }, \ + { 0xa438, 0xd503 }, \ + { 0xa438, 0xa908 }, \ + { 0xa438, 0x87f0 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x17e0 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x13c3 }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x2005 }, \ + { 0xa438, 0x8027 }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1434 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x14a5 }, \ + { 0xa438, 0xc504 }, \ + { 0xa438, 0xce20 }, \ + { 0xa438, 0xcf01 }, \ + { 0xa438, 0xd70a }, \ + { 0xa438, 0x4005 }, \ + { 0xa438, 0xcf02 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1c50 }, \ + { 0xa438, 0xa980 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x14f3 }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x67b1 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xd71e }, \ + { 0xa438, 0x65bb }, \ + { 0xa438, 0x63da }, \ + { 0xa438, 0x61f9 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c10 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0808 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0470 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0430 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0410 }, \ + { 0xa438, 0xf02a }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c20 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0804 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0470 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0430 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0420 }, \ + { 0xa438, 0xf01c }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c40 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0802 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0470 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0450 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0440 }, \ + { 0xa438, 0xf00e }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0c80 }, \ + { 0xa438, 0xd505 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0801 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce01 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x04b0 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0490 }, \ + { 0xa438, 0x0cf0 }, \ + { 0xa438, 0x0480 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0xce00 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xc48e }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1a41 }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x5faf }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0x8e01 }, \ + { 0xa438, 0x8c0f }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x17e0 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xd718 }, \ + { 0xa438, 0x4074 }, \ + { 0xa438, 0x6195 }, \ + { 0xa438, 0xf005 }, \ + { 0xa438, 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0xb88e, 0xc29f }, \ + { 0xb890, 0xad45 }, \ + { 0xb88e, 0xc2a0 }, \ + { 0xb890, 0x6640 }, \ + { 0xb88e, 0xc2a1 }, \ + { 0xb890, 0x664a }, \ + { 0xb88e, 0xc2a2 }, \ + { 0xb890, 0xa646 }, \ + { 0xb88e, 0xc2a3 }, \ + { 0xb890, 0xa650 }, \ + { 0xb88e, 0xc2a4 }, \ + { 0xb890, 0x624c }, \ + { 0xb88e, 0xc2a5 }, \ + { 0xb890, 0x6256 }, \ + { 0xb88e, 0xc2a6 }, \ + { 0xb890, 0xa453 }, \ + { 0xb88e, 0xc2a7 }, \ + { 0xb890, 0xa45d }, \ + { 0xb88e, 0xc2a8 }, \ + { 0xb890, 0x665a }, \ + { 0xb88e, 0xc2a9 }, \ + { 0xb890, 0x6664 }, \ + { 0xb88e, 0xc2aa }, \ + { 0xb890, 0xac62 }, \ + { 0xb88e, 0xc2ab }, \ + { 0xb890, 0xac6c }, \ + { 0xb88e, 0xc2ac }, \ + { 0xb890, 0x746a }, \ + { 0xb88e, 0xc2ad }, \ + { 0xb890, 0x7474 }, \ + { 0xb88e, 0xc2ae }, \ + { 0xb890, 0xbcfa }, \ + { 0xb88e, 0xc2af }, \ + { 0xb890, 0xbcfd }, \ + { 0xb88e, 0xc2b0 }, \ + { 0xb890, 0x79ff }, \ + { 0xb88e, 0xc2b1 }, \ + { 0xb890, 0x7901 }, \ + { 0xb88e, 0xc2b2 }, \ + { 0xb890, 0xf703 }, \ + { 0xb88e, 0xc2b3 }, \ + { 0xb890, 0xf706 }, \ + { 0xb88e, 0xc2b4 }, \ + { 0xb890, 0x7408 }, \ + { 0xb88e, 0xc2b5 }, \ + { 0xb890, 0x740a }, \ + { 0xb88e, 0xc2b6 }, \ + { 0xb890, 0xf10c }, \ + { 0xb88e, 0xc2b7 }, \ + { 0xb890, 0xf10f }, \ + { 0xb88e, 0xc2b8 }, \ + { 0xb890, 0x6f10 }, \ + { 0xb88e, 0xc2b9 }, \ + { 0xb890, 0x6f13 }, \ + { 0xb88e, 0xc2ba }, \ + { 0xb890, 0xec15 }, \ + { 0xb88e, 0xc2bb }, \ + { 0xb890, 0xec18 }, \ + { 0xb88e, 0xc2bc }, \ + { 0xb890, 0x6a1a }, \ + { 0xb88e, 0xc2bd }, \ + { 0xb890, 0x6a1c }, \ + { 0xb88e, 0xc2be }, \ + { 0xb890, 0xe71e }, \ + { 0xb88e, 0xc2bf }, \ + { 0xb890, 0xe721 }, \ + { 0xb88e, 0xc2c0 }, \ + { 0xb890, 0x6424 }, \ + { 0xb88e, 0xc2c1 }, \ + { 0xb890, 0x6425 }, \ + { 0xb88e, 0xc2c2 }, \ + { 0xb890, 0xe228 }, \ + { 0xb88e, 0xc2c3 }, \ + { 0xb890, 0xe22a }, \ + { 0xb88e, 0xc2c4 }, \ + { 0xb890, 0x5f2b }, \ + { 0xb88e, 0xc2c5 }, \ + { 0xb890, 0x5f2e }, \ + { 0xb88e, 0xc2c6 }, \ + { 0xb890, 0xdc31 }, \ + { 0xb88e, 0xc2c7 }, \ + { 0xb890, 0xdc33 }, \ + { 0xb88e, 0xc2c8 }, \ + { 0xb890, 0x2035 }, \ + { 0xb88e, 0xc2c9 }, \ + { 0xb890, 0x2036 }, \ + { 0xb88e, 0xc2ca }, \ + { 0xb890, 0x9f3a }, \ + { 0xb88e, 0xc2cb }, \ + { 0xb890, 0x9f3a }, \ + { 0xb88e, 0xc2cc }, \ + { 0xb890, 0x4430 }, \ + { 0xa436, 0xacca }, \ + { 0xa438, 0x0104 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x8000 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfd47 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xe56f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01c0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xed97 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01c8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xf5bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01d0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb07 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb0f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01d8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa087 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0180 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa00f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0108 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa807 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa88f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0188 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb027 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0120 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb02f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0128 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb847 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0140 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb84f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0148 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb17 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb1f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa017 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0110 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa01f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0118 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa837 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0130 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa83f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0138 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb097 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0190 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb05f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0158 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb857 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0150 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb89f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0198 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb27 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb2f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8087 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0180 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x800f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0108 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8807 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x888f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0188 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9027 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0120 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x902f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0128 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9847 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0140 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x984f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0148 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa0a7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa8af }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xa86f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb37 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb3f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8017 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0110 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x801f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0118 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8837 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0130 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x883f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0138 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9097 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0190 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x905f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0158 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9857 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0150 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x989f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0198 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb0b7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb8bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xb87f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0179 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb47 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb4f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6087 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0180 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x600f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0108 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6807 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x688f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0188 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7027 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0120 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x702f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0128 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7847 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0140 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x784f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0148 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x80a7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x88af }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x886f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb57 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb5f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6017 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0110 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x601f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0118 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6837 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0130 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x683f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0138 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7097 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0190 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x705f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0158 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7857 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0150 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x789f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0198 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x90b7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x98bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x987f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0179 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb67 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb6f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x4087 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0180 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x400f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0108 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x4807 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x488f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0188 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x5027 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0120 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x502f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0128 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x5847 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0140 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x584f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0148 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x60a7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x68af }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x686f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb77 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb7f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x4017 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0110 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x401f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0118 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x4837 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0130 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x483f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0138 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x5097 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0190 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x505f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0158 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x5857 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0150 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x589f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0198 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x70b7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x78bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x787f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0179 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb87 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb8f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x40a7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x48af }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x4067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x486f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb97 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb9f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x50b7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x58bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x5077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x587f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0179 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfba7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfbaf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x2067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x286f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfbb7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfbbf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x3077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x387f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0179 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfff9 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfff9 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfff8 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb47 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb4f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6087 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0180 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x600f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0108 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6807 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x688f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0188 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7027 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0120 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x702f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0128 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7847 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0140 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x784f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0148 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x80a7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x88af }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01a8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x8067 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0161 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x886f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0169 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb57 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0xfb5f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6017 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0110 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x601f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0118 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6837 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0130 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x683f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0138 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7097 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0190 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x705f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0158 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7857 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0150 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x789f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x0198 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x90b7 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b0 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x98bf }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x01b8 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x9077 }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x1171 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x987f }, \ + { 0xa436, 0xacd0 }, \ + { 0xa438, 0x1179 }, \ + { 0xa436, 0xacca }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xacc6 }, \ + { 0xa438, 0x0008 }, \ + { 0xa436, 0xacc8 }, \ + { 0xa438, 0xc000 }, \ + { 0xa436, 0xacc6 }, \ + { 0xa438, 0x0015 }, \ + { 0xa436, 0xacc8 }, \ + { 0xa438, 0xc043 }, \ + { 0xa436, 0xacc8 }, \ + { 0xa438, 0x0000 }, \ + { 0xb820, 0x0000 } + +#define MAC_R26_MCU \ + { 0xa436, 0x8023 }, \ + { 0xa438, 0x4700 }, \ + { 0xa436, 0xb82e }, \ + { 0xa438, 0x0001 }, \ + { 0xb820, 0x0090 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8025 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8033 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8037 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x803c }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8044 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8054 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8059 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9b5 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x4070 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x107a }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc994 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x60d0 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x252d }, \ + { 0xa438, 0x8023 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1064 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x107a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1052 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9d0 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x60d0 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x252d }, \ + { 0xa438, 0x8031 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1171 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x1187 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x116a }, \ + { 0xa438, 0xc0ff }, \ + { 0xa438, 0xcaff }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x00d6 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xa001 }, \ + { 0xa438, 0xd704 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x128b }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x2005 }, \ + { 0xa438, 0x8042 }, \ + { 0xa438, 0xd75e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x137a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x13ed }, \ + { 0xa438, 0x61d0 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x60a5 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9b2 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xf004 }, \ + { 0xa438, 0xd504 }, \ + { 0xa438, 0xc9b1 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xd707 }, \ + { 0xa438, 0x6070 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x10a8 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x10bd }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0xc492 }, \ + { 0xa438, 0xd501 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x13c1 }, \ + { 0xa438, 0xa980 }, \ + { 0xa438, 0xd500 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x143b }, \ + { 0xa436, 0xa026 }, \ + { 0xa438, 0x143a }, \ + { 0xa436, 0xa024 }, \ + { 0xa438, 0x13c0 }, \ + { 0xa436, 0xa022 }, \ + { 0xa438, 0x10bc }, \ + { 0xa436, 0xa020 }, \ + { 0xa438, 0x1379 }, \ + { 0xa436, 0xa006 }, \ + { 0xa438, 0x128a }, \ + { 0xa436, 0xa004 }, \ + { 0xa438, 0x00d5 }, \ + { 0xa436, 0xa002 }, \ + { 0xa438, 0x1182 }, \ + { 0xa436, 0xa000 }, \ + { 0xa438, 0x1075 }, \ + { 0xa436, 0xa008 }, \ + { 0xa438, 0xff00 }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0010 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8015 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x801e }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8027 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8027 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8027 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8027 }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0505 }, \ + { 0xa438, 0xba01 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x015e }, \ + { 0xa438, 0x0c0f }, \ + { 0xa438, 0x0506 }, \ + { 0xa438, 0xba02 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x017c }, \ + { 0xa438, 0x9910 }, \ + { 0xa438, 0x9a03 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x02d4 }, \ + { 0xa438, 0x8580 }, \ + { 0xa438, 0xc090 }, \ + { 0xa438, 0x9a03 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x02c9 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fa3 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0067 }, \ + { 0xa436, 0xa08e }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08c }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa08a }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa088 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xa086 }, \ + { 0xa438, 0x018c }, \ + { 0xa436, 0xa084 }, \ + { 0xa438, 0x02d3 }, \ + { 0xa436, 0xa082 }, \ + { 0xa438, 0x017a }, \ + { 0xa436, 0xa080 }, \ + { 0xa438, 0x015c }, \ + { 0xa436, 0xa090 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xa016 }, \ + { 0xa438, 0x0020 }, \ + { 0xa436, 0xa012 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xa014 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8010 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8023 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8313 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x831a }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8489 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x86b9 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x86c1 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x87ad }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x124e }, \ + { 0xa438, 0x9308 }, \ + { 0xa438, 0xb201 }, \ + { 0xa438, 0xb301 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x5fe0 }, \ + { 0xa438, 0xd2ff }, \ + { 0xa438, 0xb302 }, \ + { 0xa438, 0xd200 }, \ + { 0xa438, 0xb201 }, \ + { 0xa438, 0xb309 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x5fe0 }, \ + { 0xa438, 0xd2ff }, \ + { 0xa438, 0xb302 }, \ + { 0xa438, 0xd200 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x0025 }, \ + { 0xa438, 0xd706 }, \ + { 0xa438, 0x6069 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x6421 }, \ + { 0xa438, 0xd70c }, \ + { 0xa438, 0x43ab }, \ + { 0xa438, 0x800a }, \ + { 0xa438, 0x8190 }, \ + { 0xa438, 0x8204 }, \ + { 0xa438, 0xa280 }, \ + { 0xa438, 0x8406 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0xa108 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x0c1f }, \ + { 0xa438, 0x0f19 }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd70c }, \ + { 0xa438, 0x5fb3 }, \ + { 0xa438, 0x0c03 }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x8f1f }, \ + { 0xa438, 0x9503 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd70c }, \ + { 0xa438, 0x7f33 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x11bd }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x81aa }, \ + { 0xa438, 0x8710 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x33b1 }, \ + { 0xa438, 0x8051 }, \ + { 0xa438, 0xd701 }, \ + { 0xa438, 0x60b5 }, \ + { 0xa438, 0xd706 }, \ + { 0xa438, 0x6069 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x8056 }, \ + { 0xa438, 0xa00a }, \ + { 0xa438, 0xa280 }, \ + { 0xa438, 0xa404 }, \ + { 0xa438, 0x1800 }, \ + { 0xa438, 0x80f3 }, \ + { 0xa438, 0xd173 }, \ + { 0xa438, 0xd04d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xd173 }, \ + { 0xa438, 0xd05d }, \ + { 0xa438, 0xd10d }, \ + { 0xa438, 0xd049 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5fb4 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x64f5 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x5ee7 }, \ + { 0xa438, 0xb920 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7fb4 }, \ + { 0xa438, 0x9920 }, \ + { 0xa438, 0xcb3c }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7d94 }, \ + { 0xa438, 0x6045 }, \ + { 0xa438, 0xfffa }, \ + { 0xa438, 0xb820 }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7fa5 }, \ + { 0xa438, 0x9820 }, \ + { 0xa438, 0xcb3d }, \ + { 0xa438, 0x1000 }, \ + { 0xa438, 0x1175 }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x60b5 }, \ + { 0xa438, 0xd71f }, \ + { 0xa438, 0x7bb4 }, \ + { 0xa438, 0x61b6 }, \ + { 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0xa438, 0xff04 }, \ + { 0xa438, 0xf902 }, \ + { 0xa438, 0x8943 }, \ + { 0xa438, 0xe28f }, \ + { 0xa438, 0x920c }, \ + { 0xa438, 0x245a }, \ + { 0xa438, 0xf0e3 }, \ + { 0xa438, 0x84f7 }, \ + { 0xa438, 0x5bf0 }, \ + { 0xa438, 0x1b23 }, \ + { 0xa438, 0x9e0f }, \ + { 0xa438, 0x028a }, \ + { 0xa438, 0x52ee }, \ + { 0xa438, 0x8f96 }, \ + { 0xa438, 0x0502 }, \ + { 0xa438, 0x888e }, \ + { 0xa438, 0x0287 }, \ + { 0xa438, 0xffae }, \ + { 0xa438, 0x04ee }, \ + { 0xa438, 0x8f96 }, \ + { 0xa438, 0x06fd }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xf9fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xfa1f }, \ + { 0xa438, 0x44d2 }, \ + { 0xa438, 0x04bf }, \ + { 0xa438, 0x8f7f }, \ + { 0xa438, 0xdc19 }, \ + { 0xa438, 0xdd19 }, \ + { 0xa438, 0x829f }, \ + { 0xa438, 0xf9fe }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xfb02 }, \ + { 0xa438, 0x8855 }, \ + { 0xa438, 0xad50 }, \ + { 0xa438, 0x04ee }, \ + { 0xa438, 0x8f96 }, \ + { 0xa438, 0x04ff }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xf9fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0x0289 }, \ + { 0xa438, 0x19ac }, \ + { 0xa438, 0x3009 }, \ + { 0xa438, 0xee8f }, \ + { 0xa438, 0x9607 }, \ + { 0xa438, 0x0288 }, \ + { 0xa438, 0x8eae }, \ + { 0xa438, 0x0702 }, \ + { 0xa438, 0x8a8a }, \ + { 0xa438, 0xee8f }, \ + { 0xa438, 0x9601 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xfb02 }, \ + { 0xa438, 0x8855 }, \ + { 0xa438, 0xad50 }, \ + { 0xa438, 0x04ee }, \ + { 0xa438, 0x8f96 }, \ + { 0xa438, 0x06ff }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xfae0 }, \ + { 0xa438, 0x8457 }, \ + { 0xa438, 0xe184 }, \ + { 0xa438, 0x58ef }, \ + { 0xa438, 0x64e1 }, \ + { 0xa438, 0x8f90 }, \ + { 0xa438, 0xd000 }, \ + { 0xa438, 0xef74 }, \ + { 0xa438, 0x0271 }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xee8f }, \ + { 0xa438, 0x9601 }, \ + { 0xa438, 0xee8f }, \ + { 0xa438, 0x9004 }, \ + { 0xa438, 0xee8f }, \ + { 0xa438, 0x8f40 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x0f02 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xe584 }, \ + { 0xa438, 0x5dee }, \ + { 0xa438, 0x8f91 }, \ + { 0xa438, 0x77ef }, \ + { 0xa438, 0x96fe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x69e1 }, \ + { 0xa438, 0x8f92 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x0f02 }, \ + { 0xa438, 0x72bd }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0x93bf }, \ + { 0xa438, 0x8b12 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0xbde1 }, \ + { 0xa438, 0x8f94 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x72bd }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0x95bf }, \ + { 0xa438, 0x8b18 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0xbd02 }, \ + { 0xa438, 0x71e4 }, \ + { 0xa438, 0xef47 }, \ + { 0xa438, 0xe484 }, \ + { 0xa438, 0x57e5 }, \ + { 0xa438, 0x8458 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8e0 }, \ + { 0xa438, 0x8018 }, \ + { 0xa438, 0xad25 }, \ + { 0xa438, 0x15ee }, \ + { 0xa438, 0x8f96 }, \ + { 0xa438, 0x00d0 }, \ + { 0xa438, 0x08e4 }, \ + { 0xa438, 0x8f92 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0x93e4 }, \ + { 0xa438, 0x8f94 }, \ + { 0xa438, 0xe48f }, \ + { 0xa438, 0x9502 }, \ + { 0xa438, 0x888e }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf9e2 }, \ + { 0xa438, 0x845d }, \ + { 0xa438, 0xe38f }, \ + { 0xa438, 0x910d }, \ + { 0xa438, 0x345b }, \ + { 0xa438, 0x0f1a }, \ + { 0xa438, 0x32ac }, \ + { 0xa438, 0x3c09 }, \ + { 0xa438, 0x0c34 }, \ + { 0xa438, 0x5bf0 }, \ + { 0xa438, 0xe784 }, \ + { 0xa438, 0xf7ae }, \ + { 0xa438, 0x04ee }, \ + { 0xa438, 0x84f7 }, \ + { 0xa438, 0xf0e3 }, \ + { 0xa438, 0x8f91 }, \ + { 0xa438, 0x5b0f }, \ + { 0xa438, 0x1b23 }, \ + { 0xa438, 0xac37 }, \ + { 0xa438, 0x0ae3 }, \ + { 0xa438, 0x84f7 }, \ + { 0xa438, 0x1e32 }, \ + { 0xa438, 0xe784 }, \ + { 0xa438, 0xf7ae }, \ + { 0xa438, 0x00fd }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xfaef }, \ + { 0xa438, 0x69fa }, \ + { 0xa438, 0xfbd2 }, \ + { 0xa438, 0x01d3 }, \ + { 0xa438, 0x04d6 }, \ + { 0xa438, 0x8f92 }, \ + { 0xa438, 0xd78f }, \ + { 0xa438, 0x7bef }, \ + { 0xa438, 0x97d9 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xd81b }, \ + { 0xa438, 0x109e }, \ + { 0xa438, 0x0480 }, \ + { 0xa438, 0xdcd2 }, \ + { 0xa438, 0x0016 }, \ + { 0xa438, 0x1783 }, \ + { 0xa438, 0x9fed }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xf9fa }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x79fb }, \ + { 0xa438, 0xcffb }, \ + { 0xa438, 0xd200 }, \ + { 0xa438, 0xbe00 }, \ + { 0xa438, 0x00ef }, \ + { 0xa438, 0x1229 }, \ + { 0xa438, 0x40d0 }, \ + { 0xa438, 0x041c }, \ + { 0xa438, 0x081a }, \ + { 0xa438, 0x10bf }, \ + { 0xa438, 0x8b27 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0xbd02 }, \ + { 0xa438, 0x89ee }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0x7fef }, \ + { 0xa438, 0x1249 }, \ + { 0xa438, 0x021a }, \ + { 0xa438, 0x91d8 }, \ + { 0xa438, 0x19d9 }, \ + { 0xa438, 0xef74 }, \ + { 0xa438, 0x0271 }, \ + { 0xa438, 0xccef }, \ + { 0xa438, 0x47dd }, \ + { 0xa438, 0x89dc }, \ + { 0xa438, 0x18a8 }, \ + { 0xa438, 0x0002 }, \ + { 0xa438, 0xd202 }, \ + { 0xa438, 0x8990 }, \ + { 0xa438, 0x12a2 }, \ + { 0xa438, 0x04c8 }, \ + { 0xa438, 0xffc7 }, \ + { 0xa438, 0xffef }, \ + { 0xa438, 0x97ff }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfafb }, \ + { 0xa438, 0xef79 }, \ + { 0xa438, 0xfbbf }, \ + { 0xa438, 0x8f7f }, \ + { 0xa438, 0xef12 }, \ + { 0xa438, 0x4902 }, \ + { 0xa438, 0x1a91 }, \ + { 0xa438, 0xd819 }, \ + { 0xa438, 0xd9ef }, \ + { 0xa438, 0x64bf }, \ + { 0xa438, 0x8f87 }, \ + { 0xa438, 0xef12 }, \ + { 0xa438, 0x4902 }, \ + { 0xa438, 0x1a91 }, \ + { 0xa438, 0xd819 }, \ + { 0xa438, 0xd9ef }, \ + { 0xa438, 0x7489 }, \ + { 0xa438, 0x0271 }, \ + { 0xa438, 0xb1ad }, \ + { 0xa438, 0x502c }, \ + { 0xa438, 0xef46 }, \ + { 0xa438, 0xdc19 }, \ + { 0xa438, 0xdda2 }, \ + { 0xa438, 0x0006 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x0f02 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xa201 }, \ + { 0xa438, 0x06bf }, \ + { 0xa438, 0x8b12 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0xdca2 }, \ + { 0xa438, 0x0206 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x1502 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x1802 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0x7b1a }, \ + { 0xa438, 0x92dd }, \ + { 0xa438, 0xffef }, \ + { 0xa438, 0x97ff }, \ + { 0xa438, 0xfefd }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf9f8 }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x79fb }, \ + { 0xa438, 0x028a }, \ + { 0xa438, 0xa0bf }, \ + { 0xa438, 0x8b1b }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0x9a16 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x1e02 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xac28 }, \ + { 0xa438, 0x02ae }, \ + { 0xa438, 0xf4d6 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x1b02 }, \ + { 0xa438, 0x7291 }, \ + { 0xa438, 0xae03 }, \ + { 0xa438, 0x028a }, \ + { 0xa438, 0x8ad2 }, \ + { 0xa438, 0x00d7 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xe18f }, \ + { 0xa438, 0x8f1b }, \ + { 0xa438, 0x12a1 }, \ + { 0xa438, 0x0004 }, \ + { 0xa438, 0xef67 }, \ + { 0xa438, 0xae1d }, \ + { 0xa438, 0xef12 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x2102 }, \ + { 0xa438, 0x72bd }, \ + { 0xa438, 0x12bf }, \ + { 0xa438, 0x8b24 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0xdcef }, \ + { 0xa438, 0x64ad }, \ + { 0xa438, 0x4f04 }, \ + { 0xa438, 0x7eff }, \ + { 0xa438, 0xff16 }, \ + { 0xa438, 0x0271 }, \ + { 0xa438, 0xccae }, \ + { 0xa438, 0xd7bf }, \ + { 0xa438, 0x8b2d }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0x91ff }, \ + { 0xa438, 0xef97 }, \ + { 0xa438, 0xfffc }, \ + { 0xa438, 0xfd04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xd104 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0x92d8 }, \ + { 0xa438, 0x10dc }, \ + { 0xa438, 0x1981 }, \ + { 0xa438, 0x9ff9 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfefc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xfbfa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xbf8f }, \ + { 0xa438, 0x87d0 }, \ + { 0xa438, 0x08d1 }, \ + { 0xa438, 0xff02 }, \ + { 0xa438, 0x8a7c }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0xfeff }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xef69 }, \ + { 0xa438, 0xdd19 }, \ + { 0xa438, 0x809f }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x96fe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8e0 }, \ + { 0xa438, 0x8044 }, \ + { 0xa438, 0xf624 }, \ + { 0xa438, 0xe480 }, \ + { 0xa438, 0x44fc }, \ + { 0xa438, 0x04f8 }, \ + { 0xa438, 0xe080 }, \ + { 0xa438, 0x4ff6 }, \ + { 0xa438, 0x24e4 }, \ + { 0xa438, 0x804f }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8fa }, \ + { 0xa438, 0xfbef }, \ + { 0xa438, 0x79fb }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x2a02 }, \ + { 0xa438, 0x7291 }, \ + { 0xa438, 0xbf8b }, \ + { 0xa438, 0x3302 }, \ + { 0xa438, 0x7291 }, \ + { 0xa438, 0xd68b }, \ + { 0xa438, 0x2dd7 }, \ + { 0xa438, 0x8b30 }, \ + { 0xa438, 0x0116 }, \ + { 0xa438, 0xad50 }, \ + { 0xa438, 0x0cbf }, \ + { 0xa438, 0x8b2a }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0x9abf }, \ + { 0xa438, 0x8b33 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0x9aff }, \ + { 0xa438, 0xef97 }, \ + { 0xa438, 0xfffe }, \ + { 0xa438, 0xfc04 }, \ + { 0xa438, 0xf8f9 }, \ + { 0xa438, 0xfaef }, \ + { 0xa438, 0x49f8 }, \ + { 0xa438, 0xccf8 }, \ + { 0xa438, 0xef96 }, \ + { 0xa438, 0x0272 }, \ + { 0xa438, 0x9a1f }, \ + { 0xa438, 0x22c7 }, \ + { 0xa438, 0xbd02 }, \ + { 0xa438, 0x72dc }, \ + { 0xa438, 0xac28 }, \ + { 0xa438, 0x16ac }, \ + { 0xa438, 0x3008 }, \ + { 0xa438, 0x0271 }, \ + { 0xa438, 0xe4ef }, \ + { 0xa438, 0x6712 }, \ + { 0xa438, 0xaeee }, \ + { 0xa438, 0xd700 }, \ + { 0xa438, 0x0202 }, \ + { 0xa438, 0x71ff }, \ + { 0xa438, 0xac50 }, \ + { 0xa438, 0x05ae }, \ + { 0xa438, 0xe3d7 }, \ + { 0xa438, 0x0000 }, \ + { 0xa438, 0xfcc4 }, \ + { 0xa438, 0xfcef }, \ + { 0xa438, 0x94fe }, \ + { 0xa438, 0xfdfc }, \ + { 0xa438, 0x04cc }, \ + { 0xa438, 0xc010 }, \ + { 0xa438, 0x44ac }, \ + { 0xa438, 0x0030 }, \ + { 0xa438, 0xbce0 }, \ + { 0xa438, 0x74bc }, \ + { 0xa438, 0xe0b8 }, \ + { 0xa438, 0xbce0 }, \ + { 0xa438, 0xfcbc }, \ + { 0xa438, 0xe011 }, \ + { 0xa438, 0xacb4 }, \ + { 0xa438, 0xddac }, \ + { 0xa438, 0xb6fa }, \ + { 0xa438, 0xacb4 }, \ + { 0xa438, 0xf0ac }, \ + { 0xa438, 0xba92 }, \ + { 0xa438, 0xacb4 }, \ + { 0xa438, 0xffac }, \ + { 0xa438, 0x5600 }, \ + { 0xa438, 0xacb4 }, \ + { 0xa438, 0xccac }, \ + { 0xa438, 0xb6ff }, \ + { 0xa438, 0xb034 }, \ + { 0xa436, 0xb818 }, \ + { 0xa438, 0x2ae4 }, \ + { 0xa436, 0xb81a }, \ + { 0xa438, 0x380a }, \ + { 0xa436, 0xb81c }, \ + { 0xa438, 0x3edd }, \ + { 0xa436, 0xb81e }, \ + { 0xa438, 0x41a3 }, \ + { 0xa436, 0xb850 }, \ + { 0xa438, 0x0684 }, \ + { 0xa436, 0xb852 }, \ + { 0xa438, 0x1c02 }, \ + { 0xa436, 0xb878 }, \ + { 0xa438, 0x1b70 }, \ + { 0xa436, 0xb884 }, \ + { 0xa438, 0x0633 }, \ + { 0xa436, 0xb832 }, \ + { 0xa438, 0x00ff }, \ + { 0xa436, 0xacfc }, \ + { 0xa438, 0x0100 }, \ + { 0xa436, 0xacfe }, \ + { 0xa438, 0x8000 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3c67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x47ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3e67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x67ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3067 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x87ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3267 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3467 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3667 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xefff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3867 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3a67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x000f }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3ce7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3ee7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x30e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x32e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xafff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x34e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1008 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x36ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1048 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff5 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x38ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1088 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3aff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x10c8 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1109 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0207 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1149 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2227 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1189 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4247 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x11c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6267 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1209 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1249 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2027 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1289 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4047 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x12c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6067 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1309 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8087 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1349 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa0a7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x1389 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc0c7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x13c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe0e7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x140b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0107 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x144b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2127 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x148b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4147 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x14cb }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6167 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5109 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8287 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5149 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa2a7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5189 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc2c7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x51c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe2e7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5009 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0a0f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5049 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2a2f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5089 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4a4f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x50c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6a6f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5209 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x080f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5249 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x282f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5289 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x484f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x52c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x686f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5309 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x888f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5349 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa8af }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x5389 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc8cf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x53c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe8ef }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x550b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x090f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x554b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x292f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x558b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x494f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x55cb }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x696f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9209 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8a8f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9249 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xaaaf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9289 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcacf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x92c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xeaef }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9009 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1217 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9049 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3237 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9089 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5257 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x90c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7277 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9109 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1017 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9149 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3037 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9189 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5057 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x91c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7077 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9309 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9097 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9349 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb0b7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x9389 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd0d7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x93c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf0f7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x960b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1117 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x964b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3137 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x968b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5157 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x96cb }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7177 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd309 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9297 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd349 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb2b7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd389 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd2d7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd3c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf2f7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd009 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1a1f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd049 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3a3f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd089 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5a5f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd0c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7a7f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd109 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x181f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd149 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x383f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd189 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x585f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd1c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x787f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd209 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x989f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd249 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb8bf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd289 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd8df }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd2c9 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2517 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf8ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe0 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd70b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3534 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x191f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd74b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0555 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x393f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd78b }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1576 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x595f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd7cb }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2417 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x797f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x000d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3434 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9a9f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x004d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0455 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbabf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x008d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1476 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdadf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x00cd }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2c17 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xfaf8 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe2 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x400d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3c34 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8187 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x404d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0c55 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa1a7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x408d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1c76 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc1c7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x40cd }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2c97 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe1e7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x800d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3cb4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x898f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x804d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0cd5 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa9af }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x808d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1cf6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc9cf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x80cd }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2d17 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe9ef }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xc00d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3d34 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9197 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xc04d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0d55 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb1b7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xc08d }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1d76 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd1d7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xc0cd }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2d97 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf1f7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3dbf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x999f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0ddf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb9bf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x1dff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd9df }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf9ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe1 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0002 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3d67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3f67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x77ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3167 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x97ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3367 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3567 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3767 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3967 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3b67 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3de7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3fe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x31e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x33e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x35e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x37e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x39e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x47ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x3be6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x67ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2066 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2264 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2464 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x47ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2664 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x67ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0064 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x87ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0264 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0464 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0664 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0864 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0a65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0c65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x47ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0e65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x67ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1065 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x87ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1266 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1466 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1666 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2866 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2a66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2c66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2e66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x20e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x22e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x24e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x26e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x00e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x02e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xafff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x04e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x06e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xefff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x08e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0ae5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0ce5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0ee5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x10e5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x12e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xafff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x14e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x16e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xefff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x28e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2ae6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2ce6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2ee6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x77ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2166 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2364 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2564 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2764 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x77ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0164 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x97ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0364 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0564 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0764 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0964 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0b65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0d65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0f65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x77ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1165 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x97ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1366 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1566 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1766 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2966 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2b66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2d66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2f66 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x21e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x23e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x25e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x27e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x01e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x03e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x05e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x07e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x09e4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0be5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0de5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x0fe5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x11e5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x13e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x15e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x17e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x29e6 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x87ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2be5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2de5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x2fe5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1865 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1a65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xafff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1c65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1e65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xefff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x18e5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x97ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1ae5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1ce5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1ee5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1965 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1b65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1d65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdfff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1f65 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x19e5 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1b9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1d9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x1f9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x589c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5c9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x599c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5d9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5a9c }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x100e }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5eff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x104e }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff7 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5bff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x110e }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x114e }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf817 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x120f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf836 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc3c7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x124f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe3e7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x130f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0307 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x134f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4917 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2327 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x510f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5936 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4347 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x514f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6367 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x500f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8387 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x504f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4817 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xa3a7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x520f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5836 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xcbcf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x524f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xebef }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x530f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0b0f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x534f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4917 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2b2f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x920f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5936 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4b4f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x924f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6b6f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x900f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x8b8f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x904f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4817 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xabaf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x910f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5836 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xd3d7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x914f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xf3f7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x930f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1317 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x934f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4917 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3337 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd30f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5936 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5357 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd34f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7377 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd00f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9397 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd04f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4817 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xb3b7 }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd10f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5836 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xdbdf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd14f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x0997 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xfbff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd20f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19b6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1b1f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xd24f }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4917 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3b3f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x593f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5b5f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x099f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7b7f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x19bf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x9b9f }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xbbbf }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffe3 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0004 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffa4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x27ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffa4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x47ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffa4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x67ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x58a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x0fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5ca4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x2fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x50a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x54a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x6fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x59a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x17ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5da4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x37ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x51a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x55a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x77ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5aa4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x1fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5ea4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x3fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x52a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x56a4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x7fff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5ba4 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x2a06 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x2b06 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff7 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x53ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x2a06 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0x57ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x2b06 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf615 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf63f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x069f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x16bf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd0ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x6a46 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5ff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd4ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x6b46 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff7 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd8ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x6a46 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xdcff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0x6b46 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf615 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf63f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x069f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x16bf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd1ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xaa86 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5ff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd5ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xab86 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff7 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd9ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xaa86 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xddff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xab86 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf615 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf63f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x069f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x16bf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd2ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xeac6 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5ff6 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0003 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd6ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xebc6 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff7 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xdaff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xeac6 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xfff4 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xdeff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xebc6 }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf615 }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0007 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xf63f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0017 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x069f }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0013 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x16bf }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0013 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x4fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0013 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xfffa }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd3ff }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0x5fff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0013 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xc7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xd7e7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0017 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0xe7ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xdbe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0017 }, \ + { 0xa436, 0xad00 }, \ + { 0xa438, 0x07ff }, \ + { 0xa436, 0xad02 }, \ + { 0xa438, 0xdfe7 }, \ + { 0xa436, 0xad04 }, \ + { 0xa438, 0xfffe }, \ + { 0xa436, 0xad06 }, \ + { 0xa438, 0xffff }, \ + { 0xa436, 0xad08 }, \ + { 0xa438, 0x0017 }, \ + { 0xa436, 0xacfc }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2000 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2001 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6008 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2002 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6010 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2003 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6020 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2004 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6060 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2005 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x60a0 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2006 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x60e0 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2007 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6128 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2008 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6178 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2009 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x61a8 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200a }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x61f0 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200b }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6248 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200c }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6258 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200d }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6268 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200e }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6270 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x200f }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6274 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2010 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x627c }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2011 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6284 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2012 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6294 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2013 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x629c }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2014 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x62ac }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2015 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x62bc }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2016 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x62c4 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2017 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x7000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2018 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x2019 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201a }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201b }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201c }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201d }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201e }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xaccc }, \ + { 0xa438, 0x201f }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x6000 }, \ + { 0xa436, 0xacce }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x0000 }, \ + { 0xa438, 0x0000 }, \ + { 0xb82e, 0x0000 }, \ + { 0xa436, 0x8023 }, \ + { 0xa438, 0x0000 }, \ + { 0xa436, 0x801e }, \ + { 0xa438, 0x0027 }, \ + { 0xb820, 0x0000 }, \ + { 0xb892, 0x0000 }, \ + { 0xb88e, 0xc15c }, \ + { 0xb890, 0x0303 }, \ + { 0xb890, 0x0506 }, \ + { 0xb890, 0x0807 }, \ + { 0xb890, 0x090b }, \ + { 0xb890, 0x0e12 }, \ + { 0xb890, 0x1617 }, \ + { 0xb890, 0x1c24 }, \ + { 0xb890, 0x2b37 }, \ + { 0xb890, 0x0203 }, \ + { 0xb890, 0x0304 }, \ + { 0xb890, 0x0504 }, \ + { 0xb890, 0x0506 }, \ + { 0xb890, 0x0708 }, \ + { 0xb890, 0x090a }, \ + { 0xb890, 0x0b0e }, \ + { 0xb890, 0x1013 }, \ + { 0xb890, 0x1519 }, \ + { 0xb890, 0x1d22 }, \ + { 0xb890, 0x282e }, \ + { 0xb890, 0x363e }, \ + { 0xb890, 0x474b }, \ + { 0xb88e, 0xc196 }, \ + { 0xb890, 0x3f5e }, \ + { 0xb890, 0xf834 }, \ + { 0xb890, 0x6c01 }, \ + { 0xb890, 0xa67f }, \ + { 0xb890, 0xa06c }, \ + { 0xb890, 0x043b }, \ + { 0xb890, 0x6190 }, \ + { 0xb890, 0x88db }, \ + { 0xb890, 0x9ecd }, \ + { 0xb890, 0x4dbc }, \ + { 0xb890, 0x6e0e }, \ + { 0xb890, 0x9f2d }, \ + { 0xb890, 0x2c18 }, \ + { 0xb890, 0x5e8c }, \ + { 0xb890, 0x5bfe }, \ + { 0xb890, 0x183c }, \ + { 0xb890, 0x23c9 }, \ + { 0xb890, 0x3e84 }, \ + { 0xb890, 0x3c20 }, \ + { 0xb890, 0xcc56 }, \ + { 0xb890, 0x3480 }, \ + { 0xb890, 0x0040 }, \ + { 0xb88e, 0xc00f }, \ + { 0xb890, 0x3502 }, \ + { 0xb890, 0x0203 }, \ + { 0xb890, 0x0303 }, \ + { 0xb890, 0x0404 }, \ + { 0xb890, 0x0506 }, \ + { 0xb890, 0x0607 }, \ + { 0xb890, 0x080a }, \ + { 0xb890, 0x0b0d }, \ + { 0xb890, 0x0e10 }, \ + { 0xb890, 0x1114 }, \ + { 0xb890, 0x171b }, \ + { 0xb890, 0x1f22 }, \ + { 0xb890, 0x2832 }, \ + { 0xb890, 0x0101 }, \ + { 0xb890, 0x0101 }, \ + { 0xb890, 0x0202 }, \ + { 0xb890, 0x0303 }, \ + { 0xb890, 0x0404 }, \ + { 0xb890, 0x0506 }, \ + { 0xb890, 0x0709 }, \ + { 0xb890, 0x0a0d }, \ + { 0xb88e, 0xc047 }, \ + { 0xb890, 0x365f }, \ + { 0xb890, 0xbe10 }, \ + { 0xb890, 0x84e4 }, \ + { 0xb890, 0x60e9 }, \ + { 0xb890, 0xa86a }, \ + { 0xb890, 0xf1e3 }, \ + { 0xb890, 0xf73f }, \ + { 0xb890, 0x5c02 }, \ + { 0xb890, 0x9547 }, \ + { 0xb890, 0xc30c }, \ + { 0xb890, 0xb064 }, \ + { 0xb890, 0x079a }, \ + { 0xb890, 0x1e23 }, \ + { 0xb890, 0x1b5d }, \ + { 0xb890, 0x92e7 }, \ + { 0xb890, 0x4baf }, \ + { 0xb890, 0x2386 }, \ + { 0xb890, 0x01b6 }, \ + { 0xb890, 0x6f82 }, \ + { 0xb890, 0xdc1c }, \ + { 0xb890, 0x8c92 }, \ + { 0xb88e, 0xc110 }, \ + { 0xb890, 0x0c7f }, \ + { 0xb890, 0x1014 }, \ + { 0xb890, 0x231d }, \ + { 0xb890, 0x2023 }, \ + { 0xb890, 0x2628 }, \ + { 0xb890, 0x2a2d }, \ + { 0xb890, 0x2d2c }, \ + { 0xb890, 0x2c2e }, \ + { 0xb890, 0x320d }, \ + { 0xb88e, 0xc186 }, \ + { 0xb890, 0x0306 }, \ + { 0xb890, 0x0804 }, \ + { 0xb890, 0x0406 }, \ + { 0xb890, 0x0707 }, \ + { 0xb890, 0x0709 }, \ + { 0xb890, 0x0b0f }, \ + { 0xb890, 0x161d }, \ + { 0xb890, 0x202a }, \ + { 0xb890, 0x3f5e }, \ + { 0xb88e, 0xc1c1 }, \ + { 0xb890, 0x0040 }, \ + { 0xb890, 0x5920 }, \ + { 0xb890, 0x88cd }, \ + { 0xb890, 0x1ca1 }, \ + { 0xb890, 0x3d20 }, \ + { 0xb890, 0x3ae4 }, \ + { 0xb890, 0x6a43 }, \ + { 0xb890, 0x30af }, \ + { 0xb890, 0xdd16 }, \ + { 0xb88e, 0xc283 }, \ + { 0xb890, 0x1611 }, \ + { 0xb890, 0x161c }, \ + { 0xb890, 0x2127 }, \ + { 0xb890, 0x2c32 }, \ + { 0xb890, 0x373d }, \ + { 0xb890, 0x4247 }, \ + { 0xb890, 0x4d52 }, \ + { 0xb890, 0x585a }, \ + { 0xb890, 0x0004 }, \ + { 0xb890, 0x080c }, \ + { 0xb890, 0x1014 }, \ + { 0xb890, 0x181b }, \ + { 0xb890, 0x1f23 }, \ + { 0xb890, 0x272b }, \ + { 0xb890, 0x2f33 }, \ + { 0xb890, 0x363a }, \ + { 0xb890, 0x3e42 }, \ + { 0xb890, 0x464a }, \ + { 0xb890, 0x4d51 }, \ + { 0xb890, 0x5559 }, \ + { 0xb890, 0x5d65 }, \ + { 0xb890, 0xe769 }, \ + { 0xb890, 0xeb56 }, \ + { 0xb890, 0xc04b }, \ + { 0xb890, 0xd502 }, \ + { 0xb890, 0x2fb1 }, \ + { 0xb890, 0x33b5 }, \ + { 0xb890, 0x37f8 }, \ + { 0xb890, 0xbb98 }, \ + { 0xb890, 0x7450 }, \ + { 0xb890, 0x4c48 }, \ + { 0xb890, 0x12dc }, \ + { 0xb890, 0xdcdc }, \ + { 0xb890, 0x934a }, \ + { 0xb890, 0x3e33 }, \ + { 0xb890, 0xe496 }, \ + { 0xb890, 0x724e }, \ + { 0xb890, 0x2b07 }, \ + { 0xb890, 0xe4c0 }, \ + { 0xb890, 0x9c79 }, \ + { 0xb890, 0x5512 }, \ + { 0xb88e, 0xc212 }, \ + { 0xb890, 0x2020 }, \ + { 0xb890, 0x2020 }, \ + { 0xb890, 0x2020 }, \ + { 0xb890, 0x2020 }, \ + { 0xb890, 0x2020 }, \ + { 0xb890, 0x2019 }, \ + { 0xb88e, 0xc24d }, \ + { 0xb890, 0x8400 }, \ + { 0xb890, 0x0000 }, \ + { 0xb890, 0x0000 }, \ + { 0xb890, 0x0000 }, \ + { 0xb890, 0x0000 }, \ + { 0xb890, 0x0000 }, \ + { 0xb88e, 0xc2d3 }, \ + { 0xb890, 0x5524 }, \ + { 0xb890, 0x2526 }, \ + { 0xb890, 0x2728 }, \ + { 0xb88e, 0xc2e3 }, \ + { 0xb890, 0x3323 }, \ + { 0xb890, 0x2324 }, \ + { 0xb890, 0x2425 } + +static const struct { + uint16_t reg; + uint16_t val; +} mac_r25_mcu[] = { + MAC_R25_MCU +}, mac_r25b_mcu[] = { + MAC_R25B_MCU +}, mac_r25d_mcu[] = { + MAC_R25D_MCU +}, mac_r26_mcu[] = { + MAC_R26_MCU +}; + + +#endif /* __IF_RGE_MICROCODE_H__ */ diff --git a/sys/dev/rge/if_rge_stats.h b/sys/dev/rge/if_rge_stats.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_stats.h @@ -0,0 +1,26 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __IF_RGE_STATS_H__ +#define __IF_RGE_STATS_H__ + +struct rge_softc; + +extern int rge_hw_mac_stats_fetch(struct rge_softc *, + struct rge_hw_mac_stats *); + +#endif /* __IF_RGE_STATS_H__ */ diff --git a/sys/dev/rge/if_rge_stats.c b/sys/dev/rge/if_rge_stats.c new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_stats.c @@ -0,0 +1,133 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2023-2025 Kevin Lo + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rge.c,v 1.38 2025/09/19 00:41:14 kevlo Exp $ */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include "if_rge_vendor.h" +#include "if_rgereg.h" +#include "if_rgevar.h" +#include "if_rge_debug.h" + +#include "if_rge_stats.h" + + +/** + * @brief Fetch the MAC statistics from the hardware + * + * I don't know if this can be done asynchronously (eg via + * an interrupt notification path for completion) as I + * currently don't have datasheets. OpenBSD and the + * older if_re driver both implement this using polling. + * + * Must be called with the driver lock held. + */ +int +rge_hw_mac_stats_fetch(struct rge_softc *sc, struct rge_hw_mac_stats *hws) +{ + struct rge_mac_stats *ss = &sc->sc_mac_stats; + uint32_t reg; + uint8_t command; + int i; + + RGE_ASSERT_LOCKED(sc); + + command = RGE_READ_1(sc, RGE_CMD); + if (command == 0xff || (command & RGE_CMD_RXENB) == 0) + return (ENETDOWN); + + bus_dmamap_sync(sc->sc_dmat_stats_buf, ss->map, BUS_DMASYNC_PREREAD); + +#if 0 + if (extend_stats) + re_set_mac_ocp_bit(sc, 0xEA84, (BIT_1 | BIT_0)); +#endif + + /* Program in the memory page to write data into */ + RGE_WRITE_4(sc, RGE_DTCCR_HI, RGE_ADDR_HI(ss->paddr)); + RGE_WRITE_BARRIER_4(sc, RGE_DTCCR_HI); + + (void) RGE_READ_1(sc, RGE_CMD); + + RGE_WRITE_4(sc, RGE_DTCCR_LO, RGE_ADDR_LO(ss->paddr)); + RGE_WRITE_BARRIER_4(sc, RGE_DTCCR_LO); + + /* Inform the hardware to begin stats writing */ + RGE_WRITE_4(sc, RGE_DTCCR_LO, RGE_ADDR_LO(ss->paddr) | RGE_DTCCR_CMD); + RGE_WRITE_BARRIER_4(sc, RGE_DTCCR_LO); + + for (i = 0; i < 1000; i++) { + RGE_READ_BARRIER_4(sc, RGE_DTCCR_LO); + reg = RGE_READ_4(sc, RGE_DTCCR_LO); + if ((reg & RGE_DTCCR_CMD) == 0) + break; + DELAY(10); + } + +#if 0 + if (extend_stats) + re_clear_mac_ocp_bit(sc, 0xEA84, (BIT_1 | BIT_0)); +#endif + + if ((reg & RGE_DTCCR_CMD) != 0) + return (ETIMEDOUT); + + bus_dmamap_sync(sc->sc_dmat_stats_buf, ss->map, BUS_DMASYNC_POSTREAD); + + /* Copy them out - assume host == NIC order for now for bring-up */ + if (hws != NULL) + *hws = *ss->stats; + + return (0); +} diff --git a/sys/dev/rge/if_rge_sysctl.h b/sys/dev/rge/if_rge_sysctl.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_sysctl.h @@ -0,0 +1,25 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __IF_RGE_SYSCTL_H__ +#define __IF_RGE_SYSCTL_H__ + +struct rge_softc; + +extern void rge_sysctl_attach(struct rge_softc *); + +#endif /* __IF_RGE_SYSCTL_H__ */ diff --git a/sys/dev/rge/if_rge_sysctl.c b/sys/dev/rge/if_rge_sysctl.c new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_sysctl.c @@ -0,0 +1,238 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#include + +#include +#include + +#include "if_rge_vendor.h" +#include "if_rgereg.h" +#include "if_rgevar.h" +#include "if_rge_debug.h" +#include "if_rge_sysctl.h" + +static void +rge_sysctl_drv_stats_attach(struct rge_softc *sc) +{ + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); + struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); + struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); + + /* Create stats node */ + tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "drv_stats", + CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "driver statistics"); + child = SYSCTL_CHILDREN(tree); + + /* Driver stats */ + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "transmit_call_cnt", CTLFLAG_RD, + &sc->sc_drv_stats.transmit_call_cnt, "Calls to rge_transmit"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "transmit_stopped_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.transmit_stopped_cnt, + "rge_transmit calls to a stopped interface"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "transmit_full_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.transmit_full_cnt, + "rge_transmit calls to a full tx queue"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "transmit_queued_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.transmit_queued_cnt, + "rge_transmit calls which queued a frame"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "intr_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.intr_cnt, + "incoming interrupts"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "intr_system_errcnt", + CTLFLAG_RD, &sc->sc_drv_stats.intr_system_err_cnt, + "INTR_SYSTEM_ERR interrupt leading to a hardware reset"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rxeof_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.rxeof_cnt, + "calls to rxeof() to process RX frames"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "txeof_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.txeof_cnt, + "calls to rxeof() to process TX frame completions"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "link_state_change_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.link_state_change_cnt, + "link state changes"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_task_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.tx_task_cnt, + "calls to tx_task task to send queued frames"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "recv_input_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.recv_input_cnt, + "calls to if_input to process frames"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_desc_err_multidesc", + CTLFLAG_RD, &sc->sc_drv_stats.rx_desc_err_multidesc, + "multi-descriptor RX frames (unsupported, so dropped)"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_watchdog_timeout_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.tx_watchdog_timeout_cnt, + "TX watchdog timeouts"); + + /* TX encap counters */ + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_encap_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.tx_encap_cnt, "calls to rge_encap()"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_encap_refrag_cnt", + CTLFLAG_RD, &sc->sc_drv_stats.tx_encap_refrag_cnt, + "How often rge_encap() has re-linearised TX mbufs"); + + /* TX checksum counters */ + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_encap_err_toofrag", + CTLFLAG_RD, &sc->sc_drv_stats.tx_encap_err_toofrag, + "How often rge_encap() failed to defrag a TX mbuf"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_offload_ip_csum_set", + CTLFLAG_RD, &sc->sc_drv_stats.tx_offload_ip_csum_set, + "Number of frames with TX'ed with IPv4 checksum offload set"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_offload_tcp_csum_set", + CTLFLAG_RD, &sc->sc_drv_stats.tx_offload_tcp_csum_set, + "Number of frames TX'ed with TCP checksum offload set"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_offload_udp_csum_set", + CTLFLAG_RD, &sc->sc_drv_stats.tx_offload_udp_csum_set, + "Number of frames TX'ed with UDP checksum offload set"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "tx_offload_vlan_tag_set", + CTLFLAG_RD, &sc->sc_drv_stats.tx_offload_vlan_tag_set, + "Number of frames TX'ed with VLAN offload tag set"); + + /* RX counters */ + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_ether_csum_err", + CTLFLAG_RD, &sc->sc_drv_stats.rx_ether_csum_err, + "Number of frames RX'ed with invalid ethernet CRC"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_vlan_tag", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_vlan_tag, + "Number of frames RX'ed with offload VLAN tag"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_jumbo_frag", + CTLFLAG_RD, &sc->sc_drv_stats.rx_desc_jumbo_frag, + "Number of descriptors RX'ed as part of a multi-descriptor frame"); + + /* RX checksum offload counters */ + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_ipv4_exists", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_ipv4_exists, + "Number of frames RX'ed with IPv4 checksum offload set"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_ipv4_valid", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_ipv4_valid, + "Number of frames RX'ed with IPv4 checksum offload valid"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_tcp_exists", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_tcp_exists, + "Number of frames RX'ed with TCP checksum offload set"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_tcp_valid", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_tcp_valid, + "Number of frames RX'ed with TCP checksum offload valid"); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_udp_exists", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_udp_exists, + "Number of frames RX'ed with UDP checksum offload set"); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rx_offload_csum_udp_valid", + CTLFLAG_RD, &sc->sc_drv_stats.rx_offload_csum_udp_valid, + "Number of frames RX'ed with UDP checksum offload valid"); +} + +static void +rge_sysctl_mac_stats_attach(struct rge_softc *sc) +{ + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); + struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); + struct sysctl_oid_list *child = SYSCTL_CHILDREN(tree); + struct rge_mac_stats *ss = &sc->sc_mac_stats; + + /* Create stats node */ + tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "mac_stats", + CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "mac statistics"); + child = SYSCTL_CHILDREN(tree); + + /* MAC statistics */ + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rge_tx_ok", CTLFLAG_RD, + &ss->lcl_stats.rge_tx_ok, ""); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rge_rx_ok", CTLFLAG_RD, + &ss->lcl_stats.rge_rx_ok, ""); + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rge_tx_er", CTLFLAG_RD, + &ss->lcl_stats.rge_tx_er, ""); + /* uint32_t rge_rx_er */ + + /* uint16_t rge_miss_pkt */ + /* uint16_t rge_fae */ + /* uint32_t rge_tx_1col */ + /* uint32_t rge_tx_mcol */ + + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rge_rx_ok_phy", CTLFLAG_RD, + &ss->lcl_stats.rge_rx_ok_phy, ""); + SYSCTL_ADD_QUAD(ctx, child, OID_AUTO, "rge_rx_ok_brd", CTLFLAG_RD, + &ss->lcl_stats.rge_rx_ok_brd, ""); + + /* uint32_t rge_rx_ok_mul */ + /* uint16_t rge_tx_abt */ + /* uint16_t rge_tx_undrn */ +} + +void +rge_sysctl_attach(struct rge_softc *sc) +{ + struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev); + struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev); + + SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, + "debug", CTLFLAG_RW, &sc->sc_debug, 0, + "control debugging printfs"); + + /* Stats */ + rge_sysctl_drv_stats_attach(sc); + rge_sysctl_mac_stats_attach(sc); +} diff --git a/sys/dev/rge/if_rge_vendor.h b/sys/dev/rge/if_rge_vendor.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rge_vendor.h @@ -0,0 +1,28 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2025 Adrian Chadd + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ +#ifndef __IF_RGE_VENDOR_H__ +#define __IF_RGE_VENDOR_H__ + +#define PCI_VENDOR_REALTEK 0x10ec + +#define PCI_PRODUCT_REALTEK_E3000 0x3000 +#define PCI_PRODUCT_REALTEK_RTL8125 0x8125 +#define PCI_PRODUCT_REALTEK_RTL8126 0x8126 +#define PCI_PRODUCT_REALTEK_RTL8127 0x8127 + +#endif /* __IF_RGE_VENDOR_H__ */ diff --git a/sys/dev/rge/if_rgereg.h b/sys/dev/rge/if_rgereg.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rgereg.h @@ -0,0 +1,387 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2025 Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */ + +#ifndef __IF_RGEREG_H__ +#define __IF_RGEREG_H__ + +#define RGE_PCI_BAR0 PCI_MAPREG_START +#define RGE_PCI_BAR1 (PCI_MAPREG_START + 4) +#define RGE_PCI_BAR2 (PCI_MAPREG_START + 8) + +/* For now, a single MSI message, no multi-RX/TX ring support */ +#define RGE_MSI_MESSAGES 1 + +#define RGE_MAC0 0x0000 +#define RGE_MAC4 0x0004 +#define RGE_MAR0 0x0008 +#define RGE_MAR4 0x000c +#define RGE_DTCCR_LO 0x0010 +#define RGE_DTCCR_CMD (1U << 3) +#define RGE_DTCCR_HI 0x0014 +#define RGE_TXDESC_ADDR_LO 0x0020 +#define RGE_TXDESC_ADDR_HI 0x0024 +#define RGE_INT_CFG0 0x0034 +#define RGE_CMD 0x0037 +#define RGE_IMR 0x0038 +#define RGE_ISR 0x003c +#define RGE_TXCFG 0x0040 +#define RGE_RXCFG 0x0044 +#define RGE_TIMERCNT 0x0048 +#define RGE_EECMD 0x0050 +#define RGE_CFG0 0x0051 +#define RGE_CFG1 0x0052 +#define RGE_CFG2 0x0053 +#define RGE_CFG3 0x0054 +#define RGE_CFG4 0x0055 +#define RGE_CFG5 0x0056 +#define RGE_TDFNR 0x0057 +#define RGE_TIMERINT0 0x0058 +#define RGE_TIMERINT1 0x005c +#define RGE_CSIDR 0x0064 +#define RGE_CSIAR 0x0068 +#define RGE_PHYSTAT 0x006c +#define RGE_PMCH 0x006f +#define RGE_INT_CFG1 0x007a +#define RGE_EPHYAR 0x0080 +#define RGE_TIMERINT2 0x008c +#define RGE_TXSTART 0x0090 +#define RGE_MACOCP 0x00b0 +#define RGE_PHYOCP 0x00b8 +#define RGE_DLLPR 0x00d0 +#define RGE_TWICMD 0x00d2 +#define RGE_MCUCMD 0x00d3 +#define RGE_RXMAXSIZE 0x00da +#define RGE_CPLUSCMD 0x00e0 +#define RGE_IM 0x00e2 +#define RGE_RXDESC_ADDR_LO 0x00e4 +#define RGE_RXDESC_ADDR_HI 0x00e8 +#define RGE_PPSW 0x00f2 +#define RGE_TIMERINT3 0x00f4 +#define RGE_RADMFIFO_PROTECT 0x0402 +#define RGE_INTMITI(i) (0x0a00 + (i) * 4) +#define RGE_PHYBASE 0x0a40 +#define RGE_EPHYAR_EXT_ADDR 0x0ffe +#define RGE_ADDR0 0x19e0 +#define RGE_ADDR1 0x19e4 +#define RGE_RSS_CTRL 0x4500 +#define RGE_RXQUEUE_CTRL 0x4800 +#define RGE_EEE_TXIDLE_TIMER 0x6048 + +/* Flags for register RGE_INT_CFG0 */ +#define RGE_INT_CFG0_EN 0x01 +#define RGE_INT_CFG0_TIMEOUT_BYPASS 0x02 +#define RGE_INT_CFG0_MITIGATION_BYPASS 0x04 +#define RGE_INT_CFG0_RDU_BYPASS_8126 0x10 +#define RGE_INT_CFG0_AVOID_MISS_INTR 0x40 + +/* Flags for register RGE_CMD */ +#define RGE_CMD_RXBUF_EMPTY 0x01 +#define RGE_CMD_TXENB 0x04 +#define RGE_CMD_RXENB 0x08 +#define RGE_CMD_RESET 0x10 +#define RGE_CMD_STOPREQ 0x80 + +/* Flags for register RGE_ISR */ +#define RGE_ISR_RX_OK 0x00000001 +#define RGE_ISR_RX_ERR 0x00000002 +#define RGE_ISR_TX_OK 0x00000004 +#define RGE_ISR_TX_ERR 0x00000008 +#define RGE_ISR_RX_DESC_UNAVAIL 0x00000010 +#define RGE_ISR_LINKCHG 0x00000020 +#define RGE_ISR_RX_FIFO_OFLOW 0x00000040 +#define RGE_ISR_TX_DESC_UNAVAIL 0x00000080 +#define RGE_ISR_SWI 0x00000100 +#define RGE_ISR_PCS_TIMEOUT 0x00004000 +#define RGE_ISR_SYSTEM_ERR 0x00008000 + +#define RGE_INTRS \ + (RGE_ISR_RX_OK | RGE_ISR_RX_ERR | RGE_ISR_TX_OK | \ + RGE_ISR_TX_ERR | RGE_ISR_LINKCHG | RGE_ISR_TX_DESC_UNAVAIL | \ + RGE_ISR_PCS_TIMEOUT | RGE_ISR_SYSTEM_ERR) + +#define RGE_INTRS_TIMER \ + (RGE_ISR_RX_ERR | RGE_ISR_TX_ERR | RGE_ISR_PCS_TIMEOUT | \ + RGE_ISR_SYSTEM_ERR) + +/* Flags for register RGE_TXCFG */ +#define RGE_TXCFG_HWREV 0x7cf00000 + +/* Flags for register RGE_RXCFG */ +#define RGE_RXCFG_ALLPHYS 0x00000001 +#define RGE_RXCFG_INDIV 0x00000002 +#define RGE_RXCFG_MULTI 0x00000004 +#define RGE_RXCFG_BROAD 0x00000008 +#define RGE_RXCFG_RUNT 0x00000010 +#define RGE_RXCFG_ERRPKT 0x00000020 +#define RGE_RXCFG_VLANSTRIP 0x00c00000 + +/* Flags for register RGE_EECMD */ +#define RGE_EECMD_WRITECFG 0xc0 + +/* Flags for register RGE_CFG1 */ +#define RGE_CFG1_PM_EN 0x01 +#define RGE_CFG1_SPEED_DOWN 0x10 + +/* Flags for register RGE_CFG2 */ +#define RGE_CFG2_PMSTS_EN 0x20 +#define RGE_CFG2_CLKREQ_EN 0x80 + +/* Flags for register RGE_CFG3 */ +#define RGE_CFG3_RDY_TO_L23 0x02 +#define RGE_CFG3_WOL_LINK 0x10 +#define RGE_CFG3_WOL_MAGIC 0x20 + +/* Flags for register RGE_CFG5 */ +#define RGE_CFG5_PME_STS 0x01 +#define RGE_CFG5_WOL_LANWAKE 0x02 +#define RGE_CFG5_WOL_UCAST 0x10 +#define RGE_CFG5_WOL_MCAST 0x20 +#define RGE_CFG5_WOL_BCAST 0x40 + +/* Flags for register RGE_CSIAR */ +#define RGE_CSIAR_BYTE_EN 0x0000000f +#define RGE_CSIAR_BYTE_EN_SHIFT 12 +#define RGE_CSIAR_ADDR_MASK 0x00000fff +#define RGE_CSIAR_BUSY 0x80000000 + +/* Flags for register RGE_PHYSTAT */ +#define RGE_PHYSTAT_FDX 0x0001 +#define RGE_PHYSTAT_LINK 0x0002 +#define RGE_PHYSTAT_10MBPS 0x0004 +#define RGE_PHYSTAT_100MBPS 0x0008 +#define RGE_PHYSTAT_1000MBPS 0x0010 +#define RGE_PHYSTAT_RXFLOW 0x0020 +#define RGE_PHYSTAT_TXFLOW 0x0040 +#define RGE_PHYSTAT_2500MBPS 0x0400 +#define RGE_PHYSTAT_5000MBPS 0x1000 +#define RGE_PHYSTAT_10000MBPS 0x4000 + +/* Flags for register RGE_EPHYAR */ +#define RGE_EPHYAR_DATA_MASK 0x0000ffff +#define RGE_EPHYAR_BUSY 0x80000000 +#define RGE_EPHYAR_ADDR_MASK 0x0000007f +#define RGE_EPHYAR_ADDR_SHIFT 16 + +/* Flags for register RGE_TXSTART */ +#define RGE_TXSTART_START 0x0001 + +/* Flags for register RGE_MACOCP */ +#define RGE_MACOCP_DATA_MASK 0x0000ffff +#define RGE_MACOCP_BUSY 0x80000000 +#define RGE_MACOCP_ADDR_SHIFT 16 + +/* Flags for register RGE_PHYOCP */ +#define RGE_PHYOCP_DATA_MASK 0x0000ffff +#define RGE_PHYOCP_BUSY 0x80000000 +#define RGE_PHYOCP_ADDR_SHIFT 16 + +/* Flags for register RGE_DLLPR. */ +#define RGE_DLLPR_PFM_EN 0x40 +#define RGE_DLLPR_TX_10M_PS_EN 0x80 + +/* Flags for register RGE_MCUCMD */ +#define RGE_MCUCMD_RXFIFO_EMPTY 0x10 +#define RGE_MCUCMD_TXFIFO_EMPTY 0x20 +#define RGE_MCUCMD_IS_OOB 0x80 + +/* Flags for register RGE_CPLUSCMD */ +#define RGE_CPLUSCMD_RXCSUM 0x0020 + +#define RGE_TX_NSEGS 32 + +#define RGE_TX_LIST_CNT 1024 +#define RGE_RX_LIST_CNT 1024 + +#define RGE_ALIGN 256 +#define RGE_TX_LIST_SZ (sizeof(struct rge_tx_desc) * RGE_TX_LIST_CNT) +#define RGE_RX_LIST_SZ (sizeof(struct rge_rx_desc) * RGE_RX_LIST_CNT) +#define RGE_NEXT_TX_DESC(x) (((x) + 1) % RGE_TX_LIST_CNT) +#define RGE_NEXT_RX_DESC(x) (((x) + 1) % RGE_RX_LIST_CNT) +#define RGE_ADDR_LO(y) ((uint64_t) (y) & 0xffffffff) +#define RGE_ADDR_HI(y) ((uint64_t) (y) >> 32) + +#define RGE_ADV_2500TFDX 0x0080 +#define RGE_ADV_5000TFDX 0x0100 +#define RGE_ADV_10000TFDX 0x1000 + +/* Tx descriptor */ +struct rge_tx_desc { + uint32_t rge_cmdsts; + uint32_t rge_extsts; + uint64_t rge_addr; + uint32_t reserved[4]; +} __packed __aligned(16); + +#define RGE_TDCMDSTS_COLL 0x000f0000 +#define RGE_TDCMDSTS_EXCESSCOLL 0x00100000 +#define RGE_TDCMDSTS_TXERR 0x00800000 +#define RGE_TDCMDSTS_EOF 0x10000000 +#define RGE_TDCMDSTS_SOF 0x20000000 +#define RGE_TDCMDSTS_EOR 0x40000000 +#define RGE_TDCMDSTS_OWN 0x80000000 + +#define RGE_TDEXTSTS_VTAG 0x00020000 +#define RGE_TDEXTSTS_IPCSUM 0x20000000 +#define RGE_TDEXTSTS_TCPCSUM 0x40000000 +#define RGE_TDEXTSTS_UDPCSUM 0x80000000 + +/* Rx descriptor */ +struct rge_rx_desc { + union { + struct { + uint32_t rsvd0; + uint32_t rsvd1; + } rx_qword0; + } lo_qword0; + + union { + struct { + uint32_t rss; + uint16_t length; + uint16_t hdr_info; + } rx_qword1; + + struct { + uint32_t rsvd2; + uint32_t rsvd3; + } rx_qword2; + } lo_qword1; + + union { + uint64_t rge_addr; + + struct { + uint64_t timestamp; + } rx_timestamp; + + struct { + uint32_t rsvd4; + uint32_t rsvd5; + } rx_qword3; + } hi_qword0; + + union { + struct { + uint32_t rge_extsts; + uint32_t rge_cmdsts; + } rx_qword4; + + struct { + uint16_t rsvd6; + uint16_t rsvd7; + uint32_t rsvd8; + } rx_ptp; + } hi_qword1; +} __packed __aligned(16); + +#define RGE_RDCMDSTS_RXERRSUM 0x00100000 +#define RGE_RDCMDSTS_EOF 0x01000000 +#define RGE_RDCMDSTS_SOF 0x02000000 +#define RGE_RDCMDSTS_EOR 0x40000000 +#define RGE_RDCMDSTS_OWN 0x80000000 +#define RGE_RDCMDSTS_FRAGLEN 0x00003fff + +#define RGE_RDEXTSTS_VTAG 0x00010000 +#define RGE_RDEXTSTS_VLAN_MASK 0x0000ffff +#define RGE_RDEXTSTS_TCPCSUMERR 0x01000000 +#define RGE_RDEXTSTS_UDPCSUMERR 0x02000000 +#define RGE_RDEXTSTS_IPCSUMERR 0x04000000 +#define RGE_RDEXTSTS_TCPPKT 0x10000000 +#define RGE_RDEXTSTS_UDPPKT 0x20000000 +#define RGE_RDEXTSTS_IPV4 0x40000000 +#define RGE_RDEXTSTS_IPV6 0x80000000 + +/* + * @brief Statistics counter structure + * + * This is the layout of the hardware structure that + * is populated by the hardware when RGE_DTCCR_* is + * appropriately poked. + */ +struct rge_hw_mac_stats { + uint64_t rge_tx_ok; + uint64_t rge_rx_ok; + uint64_t rge_tx_er; + uint32_t rge_rx_er; + uint16_t rge_miss_pkt; + uint16_t rge_fae; /* frame align errors */ + uint32_t rge_tx_1col; /* one collision */ + uint32_t rge_tx_mcol; /* multple collisions */ + uint64_t rge_rx_ok_phy; /* unicast */ + uint64_t rge_rx_ok_brd; /* broadcasts */ + uint32_t rge_rx_ok_mul; /* multicasts */ + uint16_t rge_tx_abt; + uint16_t rge_tx_undrn; + + /* extended */ + uint64_t re_tx_octets; + uint64_t re_rx_octets; + uint64_t re_rx_multicast64; + uint64_t re_tx_unicast64; + uint64_t re_tx_broadcast64; + uint64_t re_tx_multicast64; + uint32_t re_tx_pause_on; + uint32_t re_tx_pause_off; + uint32_t re_tx_pause_all; + uint32_t re_tx_deferred; + uint32_t re_tx_late_collision; + uint32_t re_tx_all_collision; + uint32_t re_tx_aborted32; + uint32_t re_align_errors32; + uint32_t re_rx_frame_too_long; + uint32_t re_rx_runt; + uint32_t re_rx_pause_on; + uint32_t re_rx_pause_off; + uint32_t re_rx_pause_all; + uint32_t re_rx_unknown_opcode; + uint32_t re_rx_mac_error; + uint32_t re_tx_underrun32; + uint32_t re_rx_mac_missed; + uint32_t re_rx_tcam_dropped; + uint32_t re_tdu; + uint32_t re_rdu; + +} __packed __aligned(sizeof(uint64_t)); + +#define RGE_STATS_BUF_SIZE sizeof(struct rge_hw_mac_stats) + +#define RGE_STATS_ALIGNMENT 64 + +/* Ram version */ +#define RGE_MAC_R25D_RCODE_VER 0x0027 +#define RGE_MAC_R26_RCODE_VER 0x0033 +#define RGE_MAC_R27_RCODE_VER 0x0036 +#define RGE_MAC_R25_RCODE_VER 0x0b33 +#define RGE_MAC_R25B_RCODE_VER 0x0b99 + +#define RGE_TIMEOUT 100 + +#define RGE_JUMBO_FRAMELEN 9216 +#define RGE_JUMBO_MTU \ + (RGE_JUMBO_FRAMELEN - ETHER_HDR_LEN - ETHER_CRC_LEN - \ + ETHER_VLAN_ENCAP_LEN) + +#define RGE_TXCFG_CONFIG 0x03000700 +#define RGE_RXCFG_CONFIG 0x41000700 +#define RGE_RXCFG_CONFIG_8125B 0x41000c00 +#define RGE_RXCFG_CONFIG_8125D 0x41200c00 +#define RGE_RXCFG_CONFIG_8126 0x41200d00 + +#endif /* __IF_RGEREG_H__ */ diff --git a/sys/dev/rge/if_rgevar.h b/sys/dev/rge/if_rgevar.h new file mode 100644 --- /dev/null +++ b/sys/dev/rge/if_rgevar.h @@ -0,0 +1,269 @@ +/*- + * SPDX-License-Identifier: BSD-2-Clause + * + * Copyright (c) 2019, 2020, 2025 Kevin Lo + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +/* $OpenBSD: if_rgereg.h,v 1.15 2025/09/19 00:41:14 kevlo Exp $ */ + +#ifndef __IF_RGEVAR_H__ +#define __IF_RGEVAR_H__ + +#define RGE_LOCK(sc) (mtx_lock(&sc->sc_mtx)) +#define RGE_UNLOCK(sc) (mtx_unlock(&sc->sc_mtx)) +#define RGE_ASSERT_LOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_OWNED)) +#define RGE_ASSERT_UNLOCKED(sc) (mtx_assert(&sc->sc_mtx, MA_NOTOWNED)) + +enum rge_mac_type { + MAC_UNKNOWN = 1, + MAC_R25, + MAC_R25B, + MAC_R25D, + MAC_R26, + MAC_R27 +}; + +struct rge_drv_stats { + /* How many times if_transmit() was called */ + uint64_t transmit_call_cnt; + /* Transmitted frame failed because the interface was stopped */ + uint64_t transmit_stopped_cnt; + /* Transmitted frame failed because the TX queue is full */ + uint64_t transmit_full_cnt; + /* How many transmit frames were queued for transmit */ + uint64_t transmit_queued_cnt; + + /* How many times the interrupt routine was called */ + uint64_t intr_cnt; + /* How many times SYSTEM_ERR was set, requiring a hardware reset */ + uint64_t intr_system_err_cnt; + /* How many times rge_rxeof was called */ + uint64_t rxeof_cnt; + /* How many times rge_txeof was called */ + uint64_t txeof_cnt; + + /* How many times the link state changed */ + uint64_t link_state_change_cnt; + + /* How many times tx_task was run */ + uint64_t tx_task_cnt; + + /* Count of frames passed up into if_input() */ + uint64_t recv_input_cnt; + + /* + * For now - driver doesn't support multi descriptor + * RX frames; so count if it happens so it'll be noticed. + */ + uint64_t rx_desc_err_multidesc; + + /* + * Number of TX watchdog timeouts. + */ + uint64_t tx_watchdog_timeout_cnt; + + uint64_t tx_encap_cnt; + uint64_t tx_encap_refrag_cnt; + uint64_t tx_encap_err_toofrag; + uint64_t tx_offload_ip_csum_set; + uint64_t tx_offload_tcp_csum_set; + uint64_t tx_offload_udp_csum_set; + uint64_t tx_offload_vlan_tag_set; + + uint64_t rx_ether_csum_err; + uint64_t rx_desc_jumbo_frag; + uint64_t rx_offload_vlan_tag; + uint64_t rx_offload_csum_ipv4_exists; + uint64_t rx_offload_csum_ipv4_valid; + + uint64_t rx_offload_csum_tcp_exists; + uint64_t rx_offload_csum_tcp_valid; + + uint64_t rx_offload_csum_udp_exists; + uint64_t rx_offload_csum_udp_valid; +}; + +struct rge_txq { + struct mbuf *txq_mbuf; + bus_dmamap_t txq_dmamap; + int txq_descidx; +}; + +struct rge_rxq { + struct mbuf *rxq_mbuf; + bus_dmamap_t rxq_dmamap; +}; + +struct rge_tx { + struct rge_txq rge_txq[RGE_TX_LIST_CNT]; + int rge_txq_prodidx; + int rge_txq_considx; + + bus_addr_t rge_tx_list_paddr; + bus_dmamap_t rge_tx_list_map; + struct rge_tx_desc *rge_tx_list; +}; + +struct rge_rx { + struct rge_rxq rge_rxq[RGE_RX_LIST_CNT]; + int rge_rxq_prodidx; + int rge_rxq_considx; + +// struct if_rxring rge_rx_ring; + bus_addr_t rge_rx_list_paddr; + bus_dmamap_t rge_rx_list_map; + struct rge_rx_desc *rge_rx_list; + + struct mbuf *rge_head; + struct mbuf **rge_tail; +}; + +struct rge_queues { + struct rge_softc *q_sc; + void *q_ihc; + int q_index; + char q_name[16]; +// pci_intr_handle_t q_ih; + struct rge_tx q_tx; + struct rge_rx q_rx; +}; + +struct rge_mac_stats { + bus_addr_t paddr; + bus_dmamap_t map; + /* NIC dma buffer, NIC order */ + struct rge_hw_mac_stats *stats; + + /* Local copy for retrieval, host order */ + struct rge_hw_mac_stats lcl_stats; +}; + +struct rge_softc { + device_t sc_dev; + if_t sc_ifp; /* Ethernet common data */ + bool sc_ether_attached; + struct mtx sc_mtx; + struct resource *sc_irq[RGE_MSI_MESSAGES]; + void *sc_ih[RGE_MSI_MESSAGES]; + uint32_t sc_expcap; /* PCe exp cap */ + struct resource *sc_bres; /* bus space MMIO/IOPORT resource */ + bus_space_handle_t rge_bhandle; /* bus space handle */ + bus_space_tag_t rge_btag; /* bus space tag */ + bus_size_t rge_bsize; + bus_dma_tag_t sc_dmat; + bus_dma_tag_t sc_dmat_tx_desc; + bus_dma_tag_t sc_dmat_tx_buf; + bus_dma_tag_t sc_dmat_rx_desc; + bus_dma_tag_t sc_dmat_rx_buf; + bus_dma_tag_t sc_dmat_stats_buf; + +// pci_chipset_tag_t sc_pc; +// pcitag_t sc_tag; + struct ifmedia sc_media; /* media info */ + enum rge_mac_type rge_type; + + struct rge_queues *sc_queues; + unsigned int sc_nqueues; + + bool sc_detaching; + bool sc_stopped; + bool sc_suspended; + + /* Note: these likely should be per-TXQ */ + struct mbufq sc_txq; + struct taskqueue * sc_tq; + char sc_tq_name[32]; + char sc_tq_thr_name[32]; + struct task sc_tx_task; + + struct callout sc_timeout; /* 1 second tick */ + + uint64_t rge_mcodever; + uint16_t rge_rcodever; + uint32_t rge_flags; +#define RGE_FLAG_MSI 0x00000001 +#define RGE_FLAG_PCIE 0x00000002 + + uint32_t rge_intrs; + int rge_timerintr; +#define RGE_IMTYPE_NONE 0 +#define RGE_IMTYPE_SIM 1 + int sc_watchdog; + + uint32_t sc_debug; + + struct rge_drv_stats sc_drv_stats; + + struct rge_mac_stats sc_mac_stats; +}; + +/* + * Register space access macros. + */ +#define RGE_WRITE_4(sc, reg, val) \ + bus_space_write_4(sc->rge_btag, sc->rge_bhandle, reg, val) +#define RGE_WRITE_2(sc, reg, val) \ + bus_space_write_2(sc->rge_btag, sc->rge_bhandle, reg, val) +#define RGE_WRITE_1(sc, reg, val) \ + bus_space_write_1(sc->rge_btag, sc->rge_bhandle, reg, val) + +#define RGE_WRITE_BARRIER_4(sc, reg) \ + bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \ + BUS_SPACE_BARRIER_WRITE) +#define RGE_READ_BARRIER_4(sc, reg) \ + bus_space_barrier(sc->rge_btag, sc->rge_bhandle, reg, 4, \ + BUS_SPACE_BARRIER_READ) + + +#define RGE_READ_4(sc, reg) \ + bus_space_read_4(sc->rge_btag, sc->rge_bhandle, reg) +#define RGE_READ_2(sc, reg) \ + bus_space_read_2(sc->rge_btag, sc->rge_bhandle, reg) +#define RGE_READ_1(sc, reg) \ + bus_space_read_1(sc->rge_btag, sc->rge_bhandle, reg) + +#define RGE_SETBIT_4(sc, reg, val) \ + RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) | (val)) +#define RGE_SETBIT_2(sc, reg, val) \ + RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) | (val)) +#define RGE_SETBIT_1(sc, reg, val) \ + RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) | (val)) + +#define RGE_CLRBIT_4(sc, reg, val) \ + RGE_WRITE_4(sc, reg, RGE_READ_4(sc, reg) & ~(val)) +#define RGE_CLRBIT_2(sc, reg, val) \ + RGE_WRITE_2(sc, reg, RGE_READ_2(sc, reg) & ~(val)) +#define RGE_CLRBIT_1(sc, reg, val) \ + RGE_WRITE_1(sc, reg, RGE_READ_1(sc, reg) & ~(val)) + +#define RGE_EPHY_SETBIT(sc, reg, val) \ + rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) | (val)) + +#define RGE_EPHY_CLRBIT(sc, reg, val) \ + rge_write_ephy(sc, reg, rge_read_ephy(sc, reg) & ~(val)) + +#define RGE_PHY_SETBIT(sc, reg, val) \ + rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) | (val)) + +#define RGE_PHY_CLRBIT(sc, reg, val) \ + rge_write_phy_ocp(sc, reg, rge_read_phy_ocp(sc, reg) & ~(val)) + +#define RGE_MAC_SETBIT(sc, reg, val) \ + rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) | (val)) + +#define RGE_MAC_CLRBIT(sc, reg, val) \ + rge_write_mac_ocp(sc, reg, rge_read_mac_ocp(sc, reg) & ~(val)) + +#endif /* __IF_RGEVAR_H__ */ diff --git a/sys/modules/Makefile b/sys/modules/Makefile --- a/sys/modules/Makefile +++ b/sys/modules/Makefile @@ -348,6 +348,7 @@ ${_rdrand_rng} \ ${_rdseed_rng} \ re \ + rge \ rl \ ${_rockchip} \ rtsx \ diff --git a/sys/modules/rge/Makefile b/sys/modules/rge/Makefile new file mode 100644 --- /dev/null +++ b/sys/modules/rge/Makefile @@ -0,0 +1,7 @@ +.PATH: ${SRCTOP}/sys/dev/rge + +KMOD= if_rge +SRCS= if_rge.c if_rge_hw.c if_rge_stats.c if_rge_sysctl.c +SRCS+= device_if.h bus_if.h pci_if.h + +.include