diff --git a/sys/dev/mmc/mmc.c b/sys/dev/mmc/mmc.c --- a/sys/dev/mmc/mmc.c +++ b/sys/dev/mmc/mmc.c @@ -846,7 +846,7 @@ else if (clock <= MMC_TYPE_HS_52_MAX) { if (timing >= bus_timing_mmc_ddr52 && bus_width >= bus_width_4) - value = ext_csd[EXT_CSD_PWR_CL_52_195_DDR]; + value = ext_csd[EXT_CSD_PWR_CL_DDR_52_195]; else value = ext_csd[EXT_CSD_PWR_CL_52_195]; } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) @@ -866,12 +866,12 @@ else if (clock <= MMC_TYPE_HS_52_MAX) { if (timing == bus_timing_mmc_ddr52 && bus_width >= bus_width_4) - value = ext_csd[EXT_CSD_PWR_CL_52_360_DDR]; + value = ext_csd[EXT_CSD_PWR_CL_DDR_52_360]; else value = ext_csd[EXT_CSD_PWR_CL_52_360]; } else if (clock <= MMC_TYPE_HS200_HS400ES_MAX) { if (bus_width == bus_width_8) - value = ext_csd[EXT_CSD_PWR_CL_200_360_DDR]; + value = ext_csd[EXT_CSD_PWR_CL_DDR_200_360]; else value = ext_csd[EXT_CSD_PWR_CL_200_360]; } @@ -1800,7 +1800,7 @@ ext_csd = ivar->raw_ext_csd; rev = ext_csd[EXT_CSD_REV]; /* Handle extended capacity from EXT_CSD */ - sec_count = le32dec(&ext_csd[EXT_CSD_SEC_CNT]); + sec_count = le32dec(&ext_csd[EXT_CSD_SEC_COUNT]); if (sec_count != 0) { ivar->sec_count = sec_count; ivar->high_cap = 1; @@ -1808,47 +1808,47 @@ /* Find maximum supported bus width. */ ivar->bus_width = mmc_test_bus_width(sc); /* Get device speeds beyond normal mode. */ - card_type = ext_csd[EXT_CSD_CARD_TYPE]; - if ((card_type & EXT_CSD_CARD_TYPE_HS_52) != 0) { + card_type = ext_csd[EXT_CSD_DEVICE_TYPE]; + if ((card_type & EXT_CSD_DEVICE_TYPE_HS_52) != 0) { setbit(&ivar->timings, bus_timing_hs); ivar->hs_tran_speed = MMC_TYPE_HS_52_MAX; - } else if ((card_type & EXT_CSD_CARD_TYPE_HS_26) != 0) { + } else if ((card_type & EXT_CSD_DEVICE_TYPE_HS_26) != 0) { setbit(&ivar->timings, bus_timing_hs); ivar->hs_tran_speed = MMC_TYPE_HS_26_MAX; } - if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_2V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_DDR_52_1_2V) != 0 && (host_caps & MMC_CAP_SIGNALING_120) != 0) { setbit(&ivar->timings, bus_timing_mmc_ddr52); setbit(&ivar->vccq_120, bus_timing_mmc_ddr52); } - if ((card_type & EXT_CSD_CARD_TYPE_DDR_52_1_8V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_DDR_52_1_8V) != 0 && (host_caps & MMC_CAP_SIGNALING_180) != 0) { setbit(&ivar->timings, bus_timing_mmc_ddr52); setbit(&ivar->vccq_180, bus_timing_mmc_ddr52); } - if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_2V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS200_1_2V) != 0 && (host_caps & MMC_CAP_SIGNALING_120) != 0) { setbit(&ivar->timings, bus_timing_mmc_hs200); setbit(&ivar->vccq_120, bus_timing_mmc_hs200); } - if ((card_type & EXT_CSD_CARD_TYPE_HS200_1_8V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS200_1_8V) != 0 && (host_caps & MMC_CAP_SIGNALING_180) != 0) { setbit(&ivar->timings, bus_timing_mmc_hs200); setbit(&ivar->vccq_180, bus_timing_mmc_hs200); } - if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS400_1_2V) != 0 && (host_caps & MMC_CAP_SIGNALING_120) != 0 && ivar->bus_width == bus_width_8) { setbit(&ivar->timings, bus_timing_mmc_hs400); setbit(&ivar->vccq_120, bus_timing_mmc_hs400); } - if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS400_1_8V) != 0 && (host_caps & MMC_CAP_SIGNALING_180) != 0 && ivar->bus_width == bus_width_8) { setbit(&ivar->timings, bus_timing_mmc_hs400); setbit(&ivar->vccq_180, bus_timing_mmc_hs400); } - if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_2V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS400_1_2V) != 0 && (ext_csd[EXT_CSD_STROBE_SUPPORT] & EXT_CSD_STROBE_SUPPORT_EN) != 0 && (host_caps & MMC_CAP_SIGNALING_120) != 0 && @@ -1856,7 +1856,7 @@ setbit(&ivar->timings, bus_timing_mmc_hs400es); setbit(&ivar->vccq_120, bus_timing_mmc_hs400es); } - if ((card_type & EXT_CSD_CARD_TYPE_HS400_1_8V) != 0 && + if ((card_type & EXT_CSD_DEVICE_TYPE_HS400_1_8V) != 0 && (ext_csd[EXT_CSD_STROBE_SUPPORT] & EXT_CSD_STROBE_SUPPORT_EN) != 0 && (host_caps & MMC_CAP_SIGNALING_180) != 0 && @@ -1871,15 +1871,15 @@ ivar->cmd6_time = 500 * 1000; if (rev >= 6) ivar->cmd6_time = 10 * - ext_csd[EXT_CSD_GEN_CMD6_TIME]; + ext_csd[EXT_CSD_GENERIC_CMD6_TIME]; /* Handle HC erase sector size. */ - if (ext_csd[EXT_CSD_ERASE_GRP_SIZE] != 0) { + if (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] != 0) { ivar->erase_sector = 1024 * - ext_csd[EXT_CSD_ERASE_GRP_SIZE]; + ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]; err = mmc_switch(sc->dev, sc->dev, ivar->rca, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_ERASE_GRP_DEF, - EXT_CSD_ERASE_GRP_DEF_EN, + EXT_CSD_ERASE_GROUP_DEF, + EXT_CSD_ERASE_GROUP_DEF_EN, ivar->cmd6_time, true); if (err != MMC_ERR_NONE) { device_printf(sc->dev, diff --git a/sys/dev/mmc/mmcreg.h b/sys/dev/mmc/mmcreg.h --- a/sys/dev/mmc/mmcreg.h +++ b/sys/dev/mmc/mmcreg.h @@ -137,6 +137,8 @@ #define R1_CARD_ECC_FAILED (1u << 21) /* erx, c */ #define R1_CC_ERROR (1u << 20) /* erx, c */ #define R1_ERROR (1u << 19) /* erx, c */ +#define R1_UNDERRUN (1u << 18) /* ex, c */ +#define R1_OVERRUN (1u << 17) /* ex, c */ #define R1_CSD_OVERWRITE (1u << 16) /* erx, c */ #define R1_WP_ERASE_SKIP (1u << 15) /* erx, c */ #define R1_CARD_ECC_DISABLED (1u << 14) /* sx, a */ @@ -144,6 +146,7 @@ #define R1_CURRENT_STATE_MASK (0xfu << 9) /* sx, b */ #define R1_READY_FOR_DATA (1u << 8) /* sx, a */ #define R1_SWITCH_ERROR (1u << 7) /* sx, c */ +#define R1_EXCEPTION_EVENT (1u << 6) /* sr, a */ #define R1_APP_CMD (1u << 5) /* sr, c */ #define R1_AKE_SEQ_ERROR (1u << 3) /* er, c */ #define R1_STATUS(x) ((x) & 0xFFFFE000) @@ -158,6 +161,25 @@ #define R1_STATE_PRG 7 #define R1_STATE_DIS 8 +#define R1_SPI_IDLE (1u << 0) +#define R1_SPI_ERASE_RESET (1u << 1) +#define R1_SPI_ILLEGAL_COMMAND (1u << 2) +#define R1_SPI_COM_CRC (1u << 3) +#define R1_SPI_ERASE_SEQ (1u << 4) +#define R1_SPI_ADDRESS (1u << 5) +#define R1_SPI_PARAMETER (1u << 6) +/* R1 bit 7: always zero */ +#define R2_SPI_CARD_LOCKED (1u << 8) +#define R2_SPI_WP_ERASE_SKIP (1u << 9) +#define R2_SPI_LOCK_UNLOCK_FAIL R2_SPI_WP_ERASE_SKIP +#define R2_SPI_ERROR (1u << 10) +#define R2_SPI_CC_ERROR (1u << 11) +#define R2_SPI_CARD_ECC_ERROR (1u << 12) +#define R2_SPI_WP_VIOLATION (1u << 13) +#define R2_SPI_ERASE_PARAM (1u << 14) +#define R2_SPI_OUT_OF_RANGE (1u << 15) +#define R2_SPI_CSD_OVERWRITE R2_SPI_OUT_OF_RANGE + /* R4 responses (SDIO) */ #define R4_IO_NUM_FUNCTIONS(ocr) (((ocr) >> 28) & 0x3) #define R4_IO_MEM_PRESENT (0x1 << 27) @@ -196,7 +218,7 @@ #define MMC_DATA_READ (1UL << 1) #define MMC_DATA_STREAM (1UL << 2) #define MMC_DATA_MULTI (1UL << 3) -#define MMC_DATA_BLOCK_SIZE (1UL << 4) +#define MMC_DATA_BLOCK_SIZE (1UL << 4) struct mmc_request *mrq; size_t block_size; /* block size for CMD53 */ size_t block_count; /* block count for CMD53 */ @@ -235,18 +257,22 @@ #define MMC_SEND_CSD 9 #define MMC_SEND_CID 10 #define MMC_READ_DAT_UNTIL_STOP 11 +#define SD_SWITCH_VOLTAGE 11 #define MMC_STOP_TRANSMISSION 12 #define MMC_SEND_STATUS 13 #define MMC_BUSTEST_R 14 #define MMC_GO_INACTIVE_STATE 15 #define MMC_BUSTEST_W 19 +#define MMC_SPI_READ_OCR 58 +#define MMC_SPI_CRC_ON_OFF 59 /* Class 2: Block oriented read commands */ -#define MMC_SET_BLOCKLEN 16 -#define MMC_READ_SINGLE_BLOCK 17 -#define MMC_READ_MULTIPLE_BLOCK 18 -#define MMC_SEND_TUNING_BLOCK 19 -#define MMC_SEND_TUNING_BLOCK_HS200 21 +#define MMC_SET_BLOCKLEN 16 +#define MMC_READ_SINGLE_BLOCK 17 +#define MMC_READ_MULTIPLE_BLOCK 18 +#define MMC_SEND_TUNING_BLOCK 19 +#define MMC_SEND_TUNING_BLOCK_HS200 21 +#define SD_ADDR_EXT 22 /* Class 3: Stream write commands */ #define MMC_WRITE_DAT_UNTIL_STOP 20 @@ -347,6 +373,15 @@ /* reserved: 50 */ /* reserved: 57 */ +/* Class 11: Extension */ +#define MMC_QUE_TASK_PARAMS 44 +#define MMC_QUE_TASK_ADDR 45 +#define MMC_EXECUTE_READ_TASK 46 +#define MMC_EXECUTE_WRITE_TASK 47 +#define MMC_CMDQ_TASK_MGMT 48 +#define SD_READ_EXTR_SINGLE 48 +#define SD_WRITE_EXTR_SINGLE 49 + /* Application specific commands for SD */ #define ACMD_SET_BUS_WIDTH 6 #define ACMD_SD_STATUS 13 @@ -358,46 +393,180 @@ /* * EXT_CSD fields + * R : Read only. + * W : One time programmable and not readable. + * R/W : One time programmable and readable. + * W/E : Multiple writable with value kept after power failure, + * H/W reset assertion and any CMD0 reset and not readable. + * R/W/E : Multiple writable with value kept after power failure, + * H/W reset assertion and any CMD0 reset and readable. + * R/W/C_P : Writable after value cleared by power failure and + * HW/rest assertion (the value not cleared by CMD0 + * reset) and readable. + * R/W/E_P : Multiple writable with value reset after power + * failure, H/W reset assertion and any CMD0 reset + * and readable. + * W/E_P : Multiple writable with value reset */ -#define EXT_CSD_FLUSH_CACHE 32 /* W/E */ -#define EXT_CSD_CACHE_CTRL 33 /* R/W/E */ -#define EXT_CSD_EXT_PART_ATTR 52 /* R/W, 2 bytes */ -#define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */ -#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */ -#define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */ -#define EXT_CSD_PART_SET 155 /* R/W */ -#define EXT_CSD_PART_ATTR 156 /* R/W */ -#define EXT_CSD_PART_SUPPORT 160 /* RO */ -#define EXT_CSD_RPMB_MULT 168 /* RO */ -#define EXT_CSD_BOOT_WP_STATUS 174 /* RO */ -#define EXT_CSD_ERASE_GRP_DEF 175 /* R/W */ -#define EXT_CSD_PART_CONFIG 179 /* R/W */ -#define EXT_CSD_BUS_WIDTH 183 /* R/W */ -#define EXT_CSD_STROBE_SUPPORT 184 /* RO */ -#define EXT_CSD_HS_TIMING 185 /* R/W */ -#define EXT_CSD_POWER_CLASS 187 /* R/W */ -#define EXT_CSD_CARD_TYPE 196 /* RO */ -#define EXT_CSD_DRIVER_STRENGTH 197 /* RO */ -#define EXT_CSD_REV 192 /* RO */ -#define EXT_CSD_PART_SWITCH_TO 199 /* RO */ -#define EXT_CSD_PWR_CL_52_195 200 /* RO */ -#define EXT_CSD_PWR_CL_26_195 201 /* RO */ -#define EXT_CSD_PWR_CL_52_360 202 /* RO */ -#define EXT_CSD_PWR_CL_26_360 203 /* RO */ -#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */ -#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */ -#define EXT_CSD_ERASE_TO_MULT 223 /* RO */ -#define EXT_CSD_ERASE_GRP_SIZE 224 /* RO */ -#define EXT_CSD_BOOT_SIZE_MULT 226 /* RO */ -#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */ -#define EXT_CSD_PWR_CL_200_195 236 /* RO */ -#define EXT_CSD_PWR_CL_200_360 237 /* RO */ -#define EXT_CSD_PWR_CL_52_195_DDR 238 /* RO */ -#define EXT_CSD_PWR_CL_52_360_DDR 239 /* RO */ -#define EXT_CSD_CACHE_FLUSH_POLICY 249 /* RO */ -#define EXT_CSD_GEN_CMD6_TIME 248 /* RO */ -#define EXT_CSD_CACHE_SIZE 249 /* RO, 4 bytes */ -#define EXT_CSD_PWR_CL_200_360_DDR 253 /* RO */ +#define EXT_CSD_CMDQ_MODE_EN 15 /* R/W/E_P */ +#define EXT_CSD_SECURE_REMOVAL_TYPE 16 /* R/W & R */ +#define EXT_CSD_PRODUCT_STATE_AWARENESS_ENABLEMENT 17 /* R/W/E & R */ +#define EXT_CSD_MAX_PRE_LOADING_DATA_SIZE 18 /* R, 4 bytes */ +#define EXT_CSD_PRE_LOADING_DATA_SIZE 22 /* R/W/E_P, 4 bytes */ +#define EXT_CSD_FFU_STATUS 26 /* R */ + /* bytes 27-28 are reserved */ +#define EXT_CSD_MODE_OPERATION_CODES 29 /* W/E_P */ +#define EXT_CSD_MODE_CONFIG 30 /* R/W/E_P */ +#define EXT_CSD_BARRIER_CTRL 31 /* R/W */ +#define EXT_CSD_FLUSH_CACHE 32 /* W/E_P */ +#define EXT_CSD_CACHE_CTRL 33 /* R/W/E_P */ +#define EXT_CSD_POWER_OFF_NOTIFICATION 34 /* R/W/E_P */ +#define EXT_CSD_PACKED_FAILURE_INDEX 35 /* R */ +#define EXT_CSD_PACKED_COMMAND_STATUS 36 /* R */ +#define EXT_CSD_CONTEXT_CONF 37 /* R/W/E_P, 15 bytes */ +#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE 52 /* R/W, 2 bytes */ +#define EXT_CSD_EXCEPTION_EVENTS_STATUS 54 /* R, 2 bytes */ +#define EXT_CSD_EXCEPTION_EVENTS_CTRL 56 /* R/W/E_P, 2 bytes */ +#define EXT_CSD_DYNCAP_NEEDED 58 /* R */ +#define EXT_CSD_CLASS_6_CTRL 59 /* R/W/E_P */ +#define EXT_CSD_INI_TIMEOUT_EMU 60 /* R */ +#define EXT_CSD_DATA_SECTOR_SIZE 61 /* R */ +#define EXT_CSD_USE_NATIVE_SECTOR 62 /* R/W */ +#define EXT_CSD_NATIVE_SECTOR_SIZE 63 /* R */ +#define EXT_CSD_VENDOR_SPECIFIC_FIELD 64 /* , 64 bytes */ + /* bytes 128-129 are reserved */ +#define EXT_CSD_PROGRAM_CID_CSD_DDR_SUPPORT 130 /* R */ +#define EXT_CSD_PERIODIC_WAKEUP 131 /* R/W/E */ +#define EXT_CSD_TCASE_SUPPORT 132 /* W/E_P */ +#define EXT_CSD_PRODUCTION_STATE_AWARENESS 133 /* R/W/E */ +#define EXT_CSD_SEC_BAD_BLK_MGMNT 134 /* R/W */ + /* byte 135 is reserved */ +#define EXT_CSD_ENH_START_ADDR 136 /* R/W, 4 bytes */ +#define EXT_CSD_ENH_SIZE_MULT 140 /* R/W, 3 bytes */ +#define EXT_CSD_GP_SIZE_MULT 143 /* R/W, 12 bytes */ +#define EXT_CSD_PARTITION_SETTING_COMPLETED 155 /* R/W */ +#define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */ +#define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R, 3 bytes */ +#define EXT_CSD_PARTITIONING_SUPPORT 160 /* R */ +#define EXT_CSD_HPI_MGMT 161 /* R/W/E_P */ +#define EXT_CSD_RST_N_FUNCTION 162 /* R/W */ +#define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */ +#define EXT_CSD_BKOPS_START 164 /* W/E_P */ +#define EXT_CSD_SANITIZE_START 165 /* W/E_P */ +#define EXT_CSD_WR_REL_PARAM 166 /* R */ +#define EXT_CSD_WR_REL_SET 167 /* R/W */ +#define EXT_CSD_RPMB_SIZE_MULT 168 /* R */ +#define EXT_CSD_FW_CONFIG 169 /* R/W */ + /* byte 170 is reserved */ +#define EXT_CSD_USER_WP 171 /* R/W, R/W/C_P & R/W/E_P */ + /* byte 172 is reserved */ +#define EXT_CSD_BOOT_WP 173 /* R/W & R/W/C_P */ +#define EXT_CSD_BOOT_WP_STATUS 174 /* R */ +#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W/E_P */ + /* byte 176 is reserved */ +#define EXT_CSD_BOOT_BUS_CONDITIONS 177 /* R/W/E */ +#define EXT_CSD_BOOT_CONFIG_PROT 178 /* R/W & R/W/C_P */ +#define EXT_CSD_PARTITION_CONFIG 179 /* R/W/E & R/W/E_P */ + /* byte 180 is reserved */ +#define EXT_CSD_ERASED_MEM_CONT 181 /* R */ + /* byte 182 is reserved */ +#define EXT_CSD_BUS_WIDTH 183 /* W/E_P */ +#define EXT_CSD_STROBE_SUPPORT 184 /* R */ +#define EXT_CSD_HS_TIMING 185 /* R/W/E_P */ + /* byte 186 is reserved */ +#define EXT_CSD_POWER_CLASS 187 /* R/W/E_P */ + /* byte 188 is reserved */ +#define EXT_CSD_CMD_SET_REV 189 /* R */ + /* byte 190 is reserved */ +#define EXT_CSD_CMD_SET 191 /* R/W/E_P */ +#define EXT_CSD_REV 192 /* R */ + /* byte 193 is reserved */ +#define EXT_CSD_CSD_STRUCTURE 194 /* R */ + /* byte 195 is reserved */ +#define EXT_CSD_DEVICE_TYPE 196 /* R */ +#define EXT_CSD_DRIVER_STRENGTH 197 /* R */ +#define EXT_CSD_OUT_OF_INTERRUPT_TIME 198 /* R */ +#define EXT_CSD_PARTITION_SWITCH_TIME 199 /* R */ +#define EXT_CSD_PWR_CL_52_195 200 /* R */ +#define EXT_CSD_PWR_CL_26_195 201 /* R */ +#define EXT_CSD_PWR_CL_52_360 202 /* R */ +#define EXT_CSD_PWR_CL_26_360 203 /* R */ + /* byte 204 is reserved */ +#define EXT_CSD_MIN_PERF_R_4_26 205 /* R */ +#define EXT_CSD_MIN_PERF_W_4_26 206 /* R */ +#define EXT_CSD_MIN_PERF_R_8_26_4_52 207 /* R */ +#define EXT_CSD_MIN_PERF_W_8_26_4_52 208 /* R */ +#define EXT_CSD_MIN_PERF_R_8_52 209 /* R */ +#define EXT_CSD_MIN_PERF_W_8_52 210 /* R */ +#define EXT_CSD_SECURE_WP_INFO 211 /* R */ +#define EXT_CSD_SEC_COUNT 212 /* R, 4 bytes */ +#define EXT_CSD_SLEEP_NOTIFICATION_TIME 216 /* R */ +#define EXT_CSD_S_A_TIMEOUT 217 /* R */ +#define EXT_CSD_PRODUCTION_STATE_AWARENESS_TIMEOUT 218 /* R */ +#define EXT_CSD_S_C_VCCQ 219 /* R */ +#define EXT_CSD_S_C_VCC 220 /* R */ +#define EXT_CSD_HC_WP_GRP_SIZE 221 /* R */ +#define EXT_CSD_REL_WR_SEC_C 222 /* R */ +#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* R */ +#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* R */ +#define EXT_CSD_ACC_SIZE 225 /* R */ +#define EXT_CSD_BOOT_SIZE_MULT 226 /* R */ + /* byte 227 is reserved */ +#define EXT_CSD_BOOT_INFO 228 /* R */ +#define EXT_CSD_SEC_TRIM_MULT 229 /* R */ +#define EXT_CSD_SEC_ERASE_MULT 230 /* R */ +#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* R */ +#define EXT_CSD_TRIM_MULT 232 /* R */ + /* byte 233 is reserved */ +#define EXT_CSD_MIN_PERF_DDR_R_8_52 234 /* R */ +#define EXT_CSD_MIN_PERF_DDR_W_8_52 235 /* R */ +#define EXT_CSD_PWR_CL_200_195 236 /* R */ +#define EXT_CSD_PWR_CL_200_360 237 /* R */ +#define EMMC_EXT_CSD_PWR_CL_200_130 236 /* R */ +#define EMMC_EXT_CSD_PWR_CL_200_195 237 /* R */ +#define EXT_CSD_PWR_CL_DDR_52_195 238 /* R */ +#define EXT_CSD_PWR_CL_DDR_52_360 239 /* R */ +#define EXT_CSD_CACHE_FLUSH_POLICY 240 /* R */ +#define EXT_CSD_INI_TIMEOUT_AP 241 /* R */ +#define EXT_CSD_CORRECTLY_PRG_SECTORS_NUM 242 /* R, 4 bytes */ +#define EXT_CSD_BKOPS_STATUS 246 /* R */ +#define EXT_CSD_POWER_OFF_LONG_TIME 247 /* R */ +#define EXT_CSD_GENERIC_CMD6_TIME 248 /* R */ +#define EXT_CSD_CACHE_SIZE 249 /* R, 4 bytes */ +#define EXT_CSD_PWR_CL_DDR_200_360 253 /* R */ +#define EXT_CSD_PWR_CL_DDR_200_360 253 /* R */ +#define EXT_CSD_FIRMWARE_VERSION 254 /* R, 8 bytes */ +#define EXT_CSD_DEVICE_VERSION 262 /* R, 2 bytes */ +#define EXT_CSD_OPTIMAL_TRIM_UNIT_SIZE 264 /* R */ +#define EXT_CSD_OPTIMAL_WRITE_SIZE 265 /* R */ +#define EXT_CSD_OPTIMAL_READ_SIZE 266 /* R */ +#define EXT_CSD_PRE_EOL_INFO 267 /* R */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_A 268 /* R */ +#define EXT_CSD_DEVICE_LIFE_TIME_EST_TYP_B 269 /* R */ +#define EXT_CSD_VENDOR_PROPRIETARY_HEALTH_REPORT 270 /* R, 32 bytes */ +#define EXT_CSD_NUMBER_OF_FW_SECTORS_CORRECTLY_PROGRAMMED 302 /* R, 4 bytes */ + /* byte 306 is reserved */ +#define EXT_CSD_CMDQ_DEPTH 307 /* R */ +#define EXT_CSD_CMDQ_SUPPORT 308 /* R */ + /* bytes 309-485 are reserved */ +#define EXT_CSD_BARRIER_SUPPORT 486 /* R */ +#define EXT_CSD_FFU_ARG 487 /* R, 4 bytes */ +#define EXT_CSD_OPERATION_CODE_TIMEOUT 491 /* R */ +#define EXT_CSD_FFU_FEATURES 492 /* R */ +#define EXT_CSD_SUPPORTED_MODES 493 /* R */ +#define EXT_CSD_EXT_SUPPORT 494 /* R */ +#define EXT_CSD_LARGE_UNIT_SIZE_M1 495 /* R */ +#define EXT_CSD_CONTEXT_CAPABILITIES 496 /* R */ +#define EXT_CSD_TAG_RES_SIZE 497 /* R */ +#define EXT_CSD_TAG_UNIT_SIZE 498 /* R */ +#define EXT_CSD_DATA_TAG_SUPPORT 499 /* R */ +#define EXT_CSD_MAX_PACKED_WRITES 500 /* R */ +#define EXT_CSD_MAX_PACKED_READS 501 /* R */ +#define EXT_CSD_BKOPS_SUPPORT 502 /* R */ +#define EXT_CSD_HPI_FEATURES 503 /* R */ +#define EXT_CSD_S_CMD_SET 504 /* R */ +#define EXT_CSD_EXT_SECURITY_ERR 505 /* R */ + /* bytes 506-511 are reserved */ /* * EXT_CSD field definitions @@ -407,22 +576,22 @@ #define EXT_CSD_CACHE_CTRL_CACHE_EN 0x01 -#define EXT_CSD_EXT_PART_ATTR_DEFAULT 0x0 -#define EXT_CSD_EXT_PART_ATTR_SYSTEMCODE 0x1 -#define EXT_CSD_EXT_PART_ATTR_NPERSISTENT 0x2 +#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_DEFAULT 0x0 +#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_SYSTEMCODE 0x1 +#define EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_NPERSISTENT 0x2 -#define EXT_CSD_PART_SET_COMPLETED 0x01 +#define EXT_CSD_EXT_PARTITION_SETTING_COMPLETED 0x1 -#define EXT_CSD_PART_ATTR_ENH_USR 0x01 -#define EXT_CSD_PART_ATTR_ENH_GP0 0x02 -#define EXT_CSD_PART_ATTR_ENH_GP1 0x04 -#define EXT_CSD_PART_ATTR_ENH_GP2 0x08 -#define EXT_CSD_PART_ATTR_ENH_GP3 0x10 -#define EXT_CSD_PART_ATTR_ENH_MASK 0x1f +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_USR 0x01 +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP0 0x02 +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP1 0x04 +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP2 0x08 +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP3 0x10 +#define EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_MASK 0x1f -#define EXT_CSD_PART_SUPPORT_EN 0x01 -#define EXT_CSD_PART_SUPPORT_ENH_ATTR_EN 0x02 -#define EXT_CSD_PART_SUPPORT_EXT_ATTR_EN 0x04 +#define EXT_CSD_PARTITIONING_SUPPORT_EN 0x01 +#define EXT_CSD_PARTITIONING_SUPPORT_ENH_ATTR_EN 0x02 +#define EXT_CSD_PARTITIONING_SUPPORT_EXT_ATTR_EN 0x04 #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PWR 0x01 #define EXT_CSD_BOOT_WP_STATUS_BOOT0_PERM 0x02 @@ -431,22 +600,22 @@ #define EXT_CSD_BOOT_WP_STATUS_BOOT1_PERM 0x08 #define EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK 0x0c -#define EXT_CSD_ERASE_GRP_DEF_EN 0x01 - -#define EXT_CSD_PART_CONFIG_ACC_DEFAULT 0x00 -#define EXT_CSD_PART_CONFIG_ACC_BOOT0 0x01 -#define EXT_CSD_PART_CONFIG_ACC_BOOT1 0x02 -#define EXT_CSD_PART_CONFIG_ACC_RPMB 0x03 -#define EXT_CSD_PART_CONFIG_ACC_GP0 0x04 -#define EXT_CSD_PART_CONFIG_ACC_GP1 0x05 -#define EXT_CSD_PART_CONFIG_ACC_GP2 0x06 -#define EXT_CSD_PART_CONFIG_ACC_GP3 0x07 -#define EXT_CSD_PART_CONFIG_ACC_MASK 0x07 -#define EXT_CSD_PART_CONFIG_BOOT0 0x08 -#define EXT_CSD_PART_CONFIG_BOOT1 0x10 -#define EXT_CSD_PART_CONFIG_BOOT_USR 0x38 -#define EXT_CSD_PART_CONFIG_BOOT_MASK 0x38 -#define EXT_CSD_PART_CONFIG_BOOT_ACK 0x40 +#define EXT_CSD_ERASE_GROUP_DEF_EN 0x01 + +#define EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT 0x00 +#define EXT_CSD_PARTITION_CONFIG_ACC_BOOT0 0x01 +#define EXT_CSD_PARTITION_CONFIG_ACC_BOOT1 0x02 +#define EXT_CSD_PARTITION_CONFIG_ACC_RPMB 0x03 +#define EXT_CSD_PARTITION_CONFIG_ACC_GP0 0x04 +#define EXT_CSD_PARTITION_CONFIG_ACC_GP1 0x05 +#define EXT_CSD_PARTITION_CONFIG_ACC_GP2 0x06 +#define EXT_CSD_PARTITION_CONFIG_ACC_GP3 0x07 +#define EXT_CSD_PARTITION_CONFIG_ACC_MASK 0x07 +#define EXT_CSD_PARTITION_CONFIG_BOOT0 0x08 +#define EXT_CSD_PARTITION_CONFIG_BOOT1 0x10 +#define EXT_CSD_PARTITION_CONFIG_BOOT_USR 0x38 +#define EXT_CSD_PARTITION_CONFIG_BOOT_MASK 0x38 +#define EXT_CSD_PARTITION_CONFIG_BOOT_ACK 0x40 #define EXT_CSD_CMD_SET_NORMAL 1 #define EXT_CSD_CMD_SET_SECURE 2 @@ -463,14 +632,14 @@ #define EXT_CSD_POWER_CLASS_4BIT_MASK 0x0f #define EXT_CSD_POWER_CLASS_4BIT_SHIFT 0 -#define EXT_CSD_CARD_TYPE_HS_26 0x0001 -#define EXT_CSD_CARD_TYPE_HS_52 0x0002 -#define EXT_CSD_CARD_TYPE_DDR_52_1_8V 0x0004 -#define EXT_CSD_CARD_TYPE_DDR_52_1_2V 0x0008 -#define EXT_CSD_CARD_TYPE_HS200_1_8V 0x0010 -#define EXT_CSD_CARD_TYPE_HS200_1_2V 0x0020 -#define EXT_CSD_CARD_TYPE_HS400_1_8V 0x0040 -#define EXT_CSD_CARD_TYPE_HS400_1_2V 0x0080 +#define EXT_CSD_DEVICE_TYPE_HS_26 0x0001 +#define EXT_CSD_DEVICE_TYPE_HS_52 0x0002 +#define EXT_CSD_DEVICE_TYPE_DDR_52_1_8V 0x0004 +#define EXT_CSD_DEVICE_TYPE_DDR_52_1_2V 0x0008 +#define EXT_CSD_DEVICE_TYPE_HS200_1_8V 0x0010 +#define EXT_CSD_DEVICE_TYPE_HS200_1_2V 0x0020 +#define EXT_CSD_DEVICE_TYPE_HS400_1_8V 0x0040 +#define EXT_CSD_DEVICE_TYPE_HS400_1_2V 0x0080 #define EXT_CSD_BUS_WIDTH_1 0 #define EXT_CSD_BUS_WIDTH_4 1 @@ -571,7 +740,7 @@ #define CCCR_CC_LSC (1 << 6) #define SD_IO_CCCR_CISPTR 0x09 /* 0x09 - 0x0B */ -#define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */ +#define SD_IO_CCCR_FN0_BLKSZ 0x10 /* 0x10 - 0x11 */ #define SD_IO_CCCR_SPEED 0x13 #define CCCR_SPEED_SHS (1 << 0) #define CCCR_SPEED_BSS_MASK (0x7 << 1) @@ -585,10 +754,10 @@ /* Function Basic Registers (FBR) */ #define SD_IO_FBR_START 0x00100 /* Offset in F0 address space */ #define SD_IO_FBR_SIZE 0x00700 /* Total size of FBR */ -#define SD_IO_FBR_F_SIZE 0x00100 /* Size of each function */ -#define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE) -#define SD_IO_FBR_CIS_OFFSET 0x9 /* Offset of this function's info block within CIS area */ -#define SD_IO_FBR_IOBLKSZ 0x10 /* Block size for CMD53 block mode operations */ +#define SD_IO_FBR_F_SIZE 0x00100 /* Size of each function */ +#define SD_IO_FBR_START_F(n) (SD_IO_FBR_START + (n-1) * SD_IO_FBR_F_SIZE) +#define SD_IO_FBR_CIS_OFFSET 0x9 /* Offset of this function's info block within CIS area */ +#define SD_IO_FBR_IOBLKSZ 0x10 /* Block size for CMD53 block mode operations */ /* Card Information Structure (CIS) */ #define SD_IO_CIS_START 0x01000 /* Offset in F0 address space */ @@ -642,6 +811,7 @@ #define MMC_OCR_MAX_VOLTAGE_SHIFT 23 #define MMC_OCR_S18R (1U << 24) /* Switching to 1.8 V requested (SD) */ #define MMC_OCR_S18A MMC_OCR_S18R /* Switching to 1.8 V accepted (SD) */ +#define MMC_OCR_2T (1U << 27) /* Version 2.0 or later Transfer (SDUC) */ #define MMC_OCR_XPC (1U << 28) /* SDXC Power Control */ #define MMC_OCR_ACCESS_MODE_BYTE (0U << 29) /* Access Mode Byte (MMC) */ #define MMC_OCR_ACCESS_MODE_SECT (1U << 29) /* Access Mode Sector (MMC) */ diff --git a/sys/dev/mmc/mmcsd.c b/sys/dev/mmc/mmcsd.c --- a/sys/dev/mmc/mmcsd.c +++ b/sys/dev/mmc/mmcsd.c @@ -325,12 +325,13 @@ * Ignore user-creatable enhanced user data area and general purpose * partitions partitions as long as partitioning hasn't been finished. */ - comp = (ext_csd[EXT_CSD_PART_SET] & EXT_CSD_PART_SET_COMPLETED) != 0; + comp = (ext_csd[EXT_CSD_PARTITION_SETTING_COMPLETED] + & EXT_CSD_EXT_PARTITION_SETTING_COMPLETED) != 0; /* * Add enhanced user data area slice, unless it spans the entirety of * the user data area. The enhanced area is of a multiple of high - * capacity write protect groups ((ERASE_GRP_SIZE + HC_WP_GRP_SIZE) * + * capacity write protect groups ((HC_ERASE_GROUP_SIZE + HC_WP_GRP_SIZE) * * 512 KB) and its offset given in either sectors or bytes, depending * on whether it's a high capacity device or not. * NB: The slicer and its slices need to be registered before adding @@ -342,10 +343,11 @@ (ext_csd[EXT_CSD_ENH_SIZE_MULT + 1] << 8) + (ext_csd[EXT_CSD_ENH_SIZE_MULT + 2] << 16); if (rev >= 4 && comp == TRUE && size > 0 && - (ext_csd[EXT_CSD_PART_SUPPORT] & - EXT_CSD_PART_SUPPORT_ENH_ATTR_EN) != 0 && - (ext_csd[EXT_CSD_PART_ATTR] & (EXT_CSD_PART_ATTR_ENH_USR)) != 0) { - erase_size = ext_csd[EXT_CSD_ERASE_GRP_SIZE] * 1024 * + (ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & + EXT_CSD_PARTITIONING_SUPPORT_ENH_ATTR_EN) != 0 && + (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & + (EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_USR)) != 0) { + erase_size = ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024 * MMC_SECTOR_SIZE; wp_size = ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; size *= erase_size * wp_size; @@ -364,7 +366,7 @@ * data area in case partitions are supported. */ ro = mmc_get_read_only(dev); - mmcsd_add_part(sc, EXT_CSD_PART_CONFIG_ACC_DEFAULT, "mmcsd", + mmcsd_add_part(sc, EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT, "mmcsd", device_get_unit(dev), mmc_get_media_size(dev) * sector_size, ro); if (mmc_get_spec_vers(dev) < 3) @@ -383,26 +385,26 @@ * Determine partition switch timeout (provided in units of 10 ms) * and ensure it's at least 300 ms as some eMMC chips lie. */ - sc->part_time = max(ext_csd[EXT_CSD_PART_SWITCH_TO] * 10 * 1000, + sc->part_time = max(ext_csd[EXT_CSD_PARTITION_SWITCH_TIME] * 10 * 1000, 300 * 1000); /* Add boot partitions, which are of a fixed multiple of 128 KB. */ size = ext_csd[EXT_CSD_BOOT_SIZE_MULT] * MMC_BOOT_RPMB_BLOCK_SIZE; if (size > 0 && (mmcbr_get_caps(mmcbus) & MMC_CAP_BOOT_NOACC) == 0) { - mmcsd_add_part(sc, EXT_CSD_PART_CONFIG_ACC_BOOT0, + mmcsd_add_part(sc, EXT_CSD_PARTITION_CONFIG_ACC_BOOT0, MMCSD_FMT_BOOT, 0, size, ro | ((ext_csd[EXT_CSD_BOOT_WP_STATUS] & EXT_CSD_BOOT_WP_STATUS_BOOT0_MASK) != 0)); - mmcsd_add_part(sc, EXT_CSD_PART_CONFIG_ACC_BOOT1, + mmcsd_add_part(sc, EXT_CSD_PARTITION_CONFIG_ACC_BOOT1, MMCSD_FMT_BOOT, 1, size, ro | ((ext_csd[EXT_CSD_BOOT_WP_STATUS] & EXT_CSD_BOOT_WP_STATUS_BOOT1_MASK) != 0)); } /* Add RPMB partition, which also is of a fixed multiple of 128 KB. */ - size = ext_csd[EXT_CSD_RPMB_MULT] * MMC_BOOT_RPMB_BLOCK_SIZE; + size = ext_csd[EXT_CSD_RPMB_SIZE_MULT] * MMC_BOOT_RPMB_BLOCK_SIZE; if (rev >= 5 && size > 0) - mmcsd_add_part(sc, EXT_CSD_PART_CONFIG_ACC_RPMB, + mmcsd_add_part(sc, EXT_CSD_PARTITION_CONFIG_ACC_RPMB, MMCSD_FMT_RPMB, 0, size, ro); if (rev <= 3 || comp == FALSE) @@ -412,8 +414,9 @@ * Add general purpose partitions, which are of a multiple of high * capacity write protect groups, too. */ - if ((ext_csd[EXT_CSD_PART_SUPPORT] & EXT_CSD_PART_SUPPORT_EN) != 0) { - erase_size = ext_csd[EXT_CSD_ERASE_GRP_SIZE] * 1024 * + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] + & EXT_CSD_PARTITIONING_SUPPORT_EN) != 0) { + erase_size = ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] * 1024 * MMC_SECTOR_SIZE; wp_size = ext_csd[EXT_CSD_HC_WP_GRP_SIZE]; for (i = 0; i < MMC_PART_GP_MAX; i++) { @@ -422,7 +425,7 @@ (ext_csd[EXT_CSD_GP_SIZE_MULT + i * 3 + 2] << 16); if (size == 0) continue; - mmcsd_add_part(sc, EXT_CSD_PART_CONFIG_ACC_GP0 + i, + mmcsd_add_part(sc, EXT_CSD_PARTITION_CONFIG_ACC_GP0 + i, MMCSD_FMT_GP, i, size * erase_size * wp_size, ro); } } @@ -511,7 +514,7 @@ * of this driver while re-tuning is already paused by the disk(9) * one and vice versa. */ - if (type == EXT_CSD_PART_CONFIG_ACC_RPMB) { + if (type == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) { make_dev_args_init(&args); args.mda_flags = MAKEDEV_CHECKNAME | MAKEDEV_WAITOK; args.mda_devsw = &mmcsd_rpmb_cdevsw; @@ -559,14 +562,14 @@ } bytes = mmcsd_pretty_size(media_size, unit); - if (type == EXT_CSD_PART_CONFIG_ACC_DEFAULT) { + if (type == EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT) { speed = mmcbr_get_clock(mmcbus); printf("%s%d: %ju%sB <%s>%s at %s %d.%01dMHz/%dbit/%d-block\n", part->name, cnt, bytes, unit, mmc_get_card_id_string(dev), ro ? " (read-only)" : "", device_get_nameunit(mmcbus), speed / 1000000, (speed / 100000) % 10, mmcsd_bus_bit_width(dev), sc->max_data); - } else if (type == EXT_CSD_PART_CONFIG_ACC_RPMB) { + } else if (type == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) { printf("%s: %ju%sB partition %d%s at %s\n", part->name, bytes, unit, type, ro ? " (read-only)" : "", device_get_nameunit(dev)); @@ -574,26 +577,26 @@ enh = false; ext = NULL; extattr = 0; - if (type >= EXT_CSD_PART_CONFIG_ACC_GP0 && - type <= EXT_CSD_PART_CONFIG_ACC_GP3) { + if (type >= EXT_CSD_PARTITION_CONFIG_ACC_GP0 && + type <= EXT_CSD_PARTITION_CONFIG_ACC_GP3) { ext_csd = sc->ext_csd; - gp = type - EXT_CSD_PART_CONFIG_ACC_GP0; - if ((ext_csd[EXT_CSD_PART_SUPPORT] & - EXT_CSD_PART_SUPPORT_ENH_ATTR_EN) != 0 && - (ext_csd[EXT_CSD_PART_ATTR] & - (EXT_CSD_PART_ATTR_ENH_GP0 << gp)) != 0) + gp = type - EXT_CSD_PARTITION_CONFIG_ACC_GP0; + if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & + EXT_CSD_PARTITIONING_SUPPORT_ENH_ATTR_EN) != 0 && + (ext_csd[EXT_CSD_PARTITIONS_ATTRIBUTE] & + (EXT_CSD_PARTITIONS_ATTRIBUTE_ENH_GP0 << gp)) != 0) enh = true; - else if ((ext_csd[EXT_CSD_PART_SUPPORT] & - EXT_CSD_PART_SUPPORT_EXT_ATTR_EN) != 0) { - extattr = (ext_csd[EXT_CSD_EXT_PART_ATTR + + else if ((ext_csd[EXT_CSD_PARTITIONING_SUPPORT] & + EXT_CSD_PARTITIONING_SUPPORT_EXT_ATTR_EN) != 0) { + extattr = (ext_csd[EXT_CSD_EXT_PARTITIONS_ATTRIBUTE + (gp / 2)] >> (4 * (gp % 2))) & 0xF; switch (extattr) { - case EXT_CSD_EXT_PART_ATTR_DEFAULT: + case EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_DEFAULT: break; - case EXT_CSD_EXT_PART_ATTR_SYSTEMCODE: + case EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_SYSTEMCODE: ext = "system code"; break; - case EXT_CSD_EXT_PART_ATTR_NPERSISTENT: + case EXT_CSD_EXT_PARTITIONS_ATTRIBUTE_NPERSISTENT: ext = "non-persistent"; break; default: @@ -631,7 +634,7 @@ if (sc->enh_size == 0) return (ENXIO); - part = sc->part[EXT_CSD_PART_CONFIG_ACC_DEFAULT]; + part = sc->part[EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT]; snprintf(name, sizeof(name), "%s%d", part->disk->d_name, part->disk->d_unit); if (strcmp(name, provider) != 0) @@ -962,8 +965,8 @@ * to recover from that, especially if things go wrong. */ if (cmd.opcode == MMC_SWITCH_FUNC && dp != NULL && - (((uint8_t *)dp)[EXT_CSD_PART_CONFIG] & - EXT_CSD_PART_CONFIG_ACC_MASK) != part->type) { + (((uint8_t *)dp)[EXT_CSD_PARTITION_CONFIG] & + EXT_CSD_PARTITION_CONFIG_ACC_MASK) != part->type) { err = EINVAL; goto out; } @@ -974,7 +977,7 @@ err = mmcsd_switch_part(mmcbus, dev, rca, part->type); if (err != MMC_ERR_NONE) goto release; - if (part->type == EXT_CSD_PART_CONFIG_ACC_RPMB) { + if (part->type == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) { err = mmcsd_set_blockcount(sc, mic->blocks, mic->write_flag & (1 << 31)); if (err != MMC_ERR_NONE) @@ -986,7 +989,7 @@ (void)mmc_wait_for_app_cmd(mmcbus, dev, rca, &cmd, 0); else (void)mmc_wait_for_cmd(mmcbus, dev, &cmd, 0); - if (part->type == EXT_CSD_PART_CONFIG_ACC_RPMB) { + if (part->type == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) { /* * If the request went to the RPMB partition, try to ensure * that the command actually has completed. @@ -1004,7 +1007,7 @@ } /* * If EXT_CSD was changed, our copy is outdated now. Specifically, - * the upper bits of EXT_CSD_PART_CONFIG used in mmcsd_switch_part(), + * the upper bits of EXT_CSD_PARTITION_CONFIG used in mmcsd_switch_part(), * so retrieve EXT_CSD again. */ if (cmd.opcode == MMC_SWITCH_FUNC) { @@ -1013,13 +1016,13 @@ goto release; } switch_back: - if (part->type == EXT_CSD_PART_CONFIG_ACC_RPMB) { + if (part->type == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) { /* * If the request went to the RPMB partition, always switch * back to the default partition (see mmcsd_switch_part()). */ err = mmcsd_switch_part(mmcbus, dev, rca, - EXT_CSD_PART_CONFIG_ACC_DEFAULT); + EXT_CSD_PARTITION_CONFIG_ACC_DEFAULT); if (err != MMC_ERR_NONE) goto release; } @@ -1125,25 +1128,25 @@ * after an access in order to allow for re-tuning to take place * anew. */ - if (part == EXT_CSD_PART_CONFIG_ACC_RPMB) + if (part == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) MMCBUS_RETUNE_PAUSE(sc->mmcbus, sc->dev, true); if (sc->part_curr == part) return (MMC_ERR_NONE); - value = (sc->ext_csd[EXT_CSD_PART_CONFIG] & - ~EXT_CSD_PART_CONFIG_ACC_MASK) | part; + value = (sc->ext_csd[EXT_CSD_PARTITION_CONFIG] & + ~EXT_CSD_PARTITION_CONFIG_ACC_MASK) | part; /* Jump! */ err = mmc_switch(bus, dev, rca, EXT_CSD_CMD_SET_NORMAL, - EXT_CSD_PART_CONFIG, value, sc->part_time, true); + EXT_CSD_PARTITION_CONFIG, value, sc->part_time, true); if (err != MMC_ERR_NONE) { - if (part == EXT_CSD_PART_CONFIG_ACC_RPMB) + if (part == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) MMCBUS_RETUNE_UNPAUSE(sc->mmcbus, sc->dev); return (err); } - sc->ext_csd[EXT_CSD_PART_CONFIG] = value; - if (sc->part_curr == EXT_CSD_PART_CONFIG_ACC_RPMB) + sc->ext_csd[EXT_CSD_PARTITION_CONFIG] = value; + if (sc->part_curr == EXT_CSD_PARTITION_CONFIG_ACC_RPMB) MMCBUS_RETUNE_UNPAUSE(sc->mmcbus, sc->dev); sc->part_curr = part; return (MMC_ERR_NONE);