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Index: head/sys/amd64/pci/pci_cfgreg.c
===================================================================
--- head/sys/amd64/pci/pci_cfgreg.c
+++ head/sys/amd64/pci/pci_cfgreg.c
@@ -64,6 +64,7 @@
static int pcie_minbus, pcie_maxbus;
static uint32_t pcie_badslots;
static struct mtx pcicfg_mtx;
+MTX_SYSINIT(pcicfg_mtx, &pcicfg_mtx, "pcicfg_mtx", MTX_SPIN);
static int mcfg_enable = 1;
SYSCTL_INT(_hw_pci, OID_AUTO, mcfg, CTLFLAG_RDTUN, &mcfg_enable, 0,
"Enable support for PCI-e memory mapped config access");
@@ -74,15 +75,9 @@
int
pci_cfgregopen(void)
{
- static int once = 0;
uint64_t pciebar;
uint16_t did, vid;
- if (!once) {
- mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN);
- once = 1;
- }
-
if (cfgmech != CFGMECH_NONE)
return (1);
cfgmech = CFGMECH_1;
@@ -138,6 +133,9 @@
{
uint32_t line;
+ if (cfgmech == CFGMECH_NONE)
+ return (0xffffffff);
+
/*
* Some BIOS writers seem to want to ignore the spec and put
* 0 in the intline rather than 255 to indicate none. Some use
@@ -162,6 +160,9 @@
pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes)
{
+ if (cfgmech == CFGMECH_NONE)
+ return;
+
if (cfgmech == CFGMECH_PCIE &&
(bus >= pcie_minbus && bus <= pcie_maxbus) &&
(bus != 0 || !(1 << slot & pcie_badslots)))

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