diff --git a/cad/Makefile b/cad/Makefile index eb78c22e670e..9ac5b05745f3 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -1,150 +1,151 @@ COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += PrusaSlicer SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += appcsxcad SUBDIR += archimedes SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += camotics SUBDIR += caneda SUBDIR += cascade SUBDIR += cascade-compiler SUBDIR += chipvault SUBDIR += csxcad SUBDIR += cura SUBDIR += cura-engine SUBDIR += cvc SUBDIR += digital SUBDIR += dinotrace SUBDIR += ecpprog SUBDIR += electric SUBDIR += electric-ng SUBDIR += fasm SUBDIR += fdm_materials SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gds3d SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += graywolf SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += horizon-eda SUBDIR += ifcopenshell SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-doc SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += ktechlab SUBDIR += ldraw SUBDIR += ldview SUBDIR += leocad SUBDIR += lepton-eda SUBDIR += libgdsii SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += librepcb SUBDIR += librnd SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += meshlab SUBDIR += netgen SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade SUBDIR += opencascade740 SUBDIR += openctm SUBDIR += openfpgaloader SUBDIR += openroad SUBDIR += openscad SUBDIR += openscad-devel SUBDIR += opentimer SUBDIR += openvsp SUBDIR += oregano SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += padring SUBDIR += pcb SUBDIR += pcb-rnd SUBDIR += pdnmesh SUBDIR += py-cadquery SUBDIR += py-cq-editor SUBDIR += py-ezdxf SUBDIR += py-gdspy SUBDIR += py-gmsh SUBDIR += py-lcapy SUBDIR += py-ocp SUBDIR += py-phidl SUBDIR += py-pyfda SUBDIR += py-pygmsh SUBDIR += py-pymtl + SUBDIR += py-vunit-hdl SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qcsxcad SUBDIR += qelectrotech SUBDIR += qflow SUBDIR += qmls SUBDIR += qrouter SUBDIR += qucs-s SUBDIR += qucsator SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += stm32flash SUBDIR += sumo SUBDIR += surelog SUBDIR += svlint SUBDIR += svls SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += uhdm SUBDIR += uranium SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += veroroute SUBDIR += veryl SUBDIR += xcircuit SUBDIR += xyce SUBDIR += yosys SUBDIR += z88 SUBDIR += zcad .include diff --git a/cad/py-vunit-hdl/Makefile b/cad/py-vunit-hdl/Makefile new file mode 100644 index 000000000000..71c7d9bf9eb6 --- /dev/null +++ b/cad/py-vunit-hdl/Makefile @@ -0,0 +1,21 @@ +PORTNAME= vunit-hdl +DISTVERSION= 4.6.0 +CATEGORIES= cad python +MASTER_SITES= CHEESESHOP +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} +DISTNAME= ${PORTNAME:S/-/_/}-${PORTVERSION} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Open source unit testing framework for VHDL/SystemVerilog +WWW= https://vunit.github.io/ + +LICENSE= MPL20 + +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}colorama>0:devel/py-colorama@${PY_FLAVOR} + +USES= python:3.6+ +USE_PYTHON= distutils autoplist pytest # 2 tests fail, see https://github.com/VUnit/vunit/issues/886 + +NO_ARCH= yes + +.include diff --git a/cad/py-vunit-hdl/distinfo b/cad/py-vunit-hdl/distinfo new file mode 100644 index 000000000000..4a36e544fc44 --- /dev/null +++ b/cad/py-vunit-hdl/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1673167323 +SHA256 (vunit_hdl-4.6.0.tar.gz) = b405a97b5da4c26c99d8c726f38594c9173c0ac3f8a0832431c8e4920d2cacdf +SIZE (vunit_hdl-4.6.0.tar.gz) = 626992 diff --git a/cad/py-vunit-hdl/pkg-descr b/cad/py-vunit-hdl/pkg-descr new file mode 100644 index 000000000000..2c5b8b031639 --- /dev/null +++ b/cad/py-vunit-hdl/pkg-descr @@ -0,0 +1,5 @@ +VUnit is an open source unit testing framework for VHDL/SystemVerilog. It +features the functionality needed to realize continuous and automated +testing of your HDL code. VUnit doesn't replace but rather complements +traditional testing methodologies by supporting a test early and often +approach through automation. Read more about VUnit.