diff --git a/cad/Makefile b/cad/Makefile index fa412f520987..7d15ad17a9ab 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -1,154 +1,155 @@ COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += PrusaSlicer SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += antimony SUBDIR += appcsxcad SUBDIR += archimedes SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += camotics SUBDIR += caneda SUBDIR += cascade SUBDIR += cascade-compiler SUBDIR += chipvault SUBDIR += csxcad SUBDIR += cura SUBDIR += cura-engine SUBDIR += cvc SUBDIR += digital SUBDIR += dinotrace SUBDIR += ecpprog SUBDIR += electric SUBDIR += electric-ng SUBDIR += fasm SUBDIR += fdm_materials SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gds3d SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += graywolf SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += horizon-eda SUBDIR += ifcopenshell SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-doc SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += ktechlab SUBDIR += ldraw SUBDIR += ldview SUBDIR += leocad SUBDIR += lepton-eda SUBDIR += libgdsii SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += librepcb SUBDIR += librnd SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += meshlab SUBDIR += netgen SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade SUBDIR += opencascade740 SUBDIR += openctm SUBDIR += openfpgaloader SUBDIR += openroad SUBDIR += openscad SUBDIR += openscad-devel SUBDIR += opentimer SUBDIR += openvsp SUBDIR += oregano SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += padring SUBDIR += pcb SUBDIR += pcb-rnd SUBDIR += pdnmesh SUBDIR += py-cadquery + SUBDIR += py-cocotb SUBDIR += py-cq-editor SUBDIR += py-edalize SUBDIR += py-ezdxf SUBDIR += py-gdspy SUBDIR += py-gmsh SUBDIR += py-lcapy SUBDIR += py-ocp SUBDIR += py-phidl SUBDIR += py-pyfda SUBDIR += py-pygmsh SUBDIR += py-pymtl SUBDIR += py-vunit-hdl SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qcsxcad SUBDIR += qelectrotech SUBDIR += qflow SUBDIR += qmls SUBDIR += qrouter SUBDIR += qucs-s SUBDIR += qucsator SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += silice SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += stm32flash SUBDIR += sumo SUBDIR += surelog SUBDIR += svlint SUBDIR += svls SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += uhdm SUBDIR += uranium SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += veroroute SUBDIR += veryl SUBDIR += xcircuit SUBDIR += xyce SUBDIR += yosys SUBDIR += z88 SUBDIR += zcad .include diff --git a/cad/py-cocotb/Makefile b/cad/py-cocotb/Makefile new file mode 100644 index 000000000000..a2168ec07d4d --- /dev/null +++ b/cad/py-cocotb/Makefile @@ -0,0 +1,40 @@ +PORTNAME= cocotb +DISTVERSIONPREFIX= v +DISTVERSION= 1.7.2 +CATEGORIES= cad python +PKGNAMEPREFIX= ${PYTHON_PKGNAMEPREFIX} + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Coroutine based cosimulation library for writing VHDL and Verilog +WWW= https://www.cocotb.org/ + +LICENSE= BSD3CLAUSE +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= ${PYTHON_PKGNAMEPREFIX}wheel>0:devel/py-wheel@${PY_FLAVOR} +RUN_DEPENDS= ${PYTHON_PKGNAMEPREFIX}find-libpython>0:devel/py-find-libpython@${PY_FLAVOR} \ + gtkwave:cad/gtkwave + +USES= python:3.6+ +USE_PYTHON= pep517 autoplist pytest # https://github.com/cocotb/cocotb/issues/3230 +USE_GITHUB= yes + +TEST_ENV= ${MAKE_ENV} PYTHONPATH=${STAGEDIR}${PYTHONPREFIX_SITELIBDIR} +TEST_WRKSRC= ${WRKSRC}/tests + +OPTIONS_DEFINE= IVERILOG VERILATOR # GHDL - TODO +OPTIONS_DEFAULT= IVERILOG VERILATOR + +IVERILOG_DESC= Iverilog dependency +IVERILOG_RUN_DEPENDS= iverilog:cad/iverilog + +VERILATOR_DESC= Verilator dependency +VERILATOR_RUN_DEPENDS= verilator:cad/verilator + +post-install: + @${STRIP_CMD} \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/simulator${PYTHON_EXT_SUFFIX}.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/lib*.so \ + ${STAGEDIR}${PYTHON_SITELIBDIR}/cocotb/libs/libcocotbvpi_icarus.vpl + +.include diff --git a/cad/py-cocotb/distinfo b/cad/py-cocotb/distinfo new file mode 100644 index 000000000000..f7f52cba0128 --- /dev/null +++ b/cad/py-cocotb/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1675490974 +SHA256 (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 2b72f25e91a8733abc9a49171adcf67d04670eb64bdc6be0d8ee653ac6b1d69f +SIZE (cocotb-cocotb-v1.7.2_GH0.tar.gz) = 641521 diff --git a/cad/py-cocotb/pkg-descr b/cad/py-cocotb/pkg-descr new file mode 100644 index 000000000000..de72cfe264b0 --- /dev/null +++ b/cad/py-cocotb/pkg-descr @@ -0,0 +1,5 @@ +cocotb is an open source coroutine-based cosimulation testbench environment +for verifying VHDL and SystemVerilog RTL using Python. + +cocotb lets you verify chips like software: productive, simulator-agnostic, +in Python.