diff --git a/cad/abc/Makefile b/cad/abc/Makefile
index 4d1c0533cb5a..2dc2ef1939fb 100644
--- a/cad/abc/Makefile
+++ b/cad/abc/Makefile
@@ -1,39 +1,42 @@
 PORTNAME=	abc
-DISTVERSION=	g20241117
+DISTVERSION=	g20251002
 CATEGORIES=	cad
 
-MAINTAINER=	uddka@student.kit.edu
+MAINTAINER=	alven@FreeBSD.org
 COMMENT=	System for sequential synthesis and verification
 WWW=		https://people.eecs.berkeley.edu/~alanmi/abc/
 
 LICENSE=	MIT
 LICENSE_FILE=	${WRKSRC}/copyright.txt
 
 BUILD_DEPENDS=	gmake:devel/gmake
 
 USES=		cmake
 USE_GITHUB=	yes
 GH_ACCOUNT=	berkeley-abc
-GH_TAGNAME=	1f3cf0a
+GH_TAGNAME=	c8eac759
 USE_LDCONFIG=	yes
 
 CMAKE_ON=	ABC_SKIP_TESTS
 
 BINARY_ALIAS=	make=${GMAKE}
 
-PLIST_FILES=	bin/${PORTNAME} lib/lib${PORTNAME}.so
+PLIST_FILES=	bin/${PORTNAME} \
+		lib/lib${PORTNAME}.so
 
-OPTIONS_DEFINE=			READLINE THREADS
-OPTIONS_DEFAULT=		READLINE THREADS
+OPTIONS_DEFINE=		READLINE THREADS
+OPTIONS_DEFAULT=	READLINE THREADS
 
 READLINE_USES=			readline
 READLINE_CONFIGURE_ENV=		ABC_READLINE_LIBRARIES="-L${LOCALBASE}/lib -lreadline"
 READLINE_CONFIGURE_ENV_OFF=	ABC_USE_NO_READLINE=1
 
 THREADS_CONFIGURE_ENV_OFF=	ABC_USE_NO_PTHREADS=1
 
 do-install: # https://github.com/berkeley-abc/abc/issues/71
-	${INSTALL_PROGRAM} ${BUILD_WRKSRC}/${PORTNAME} ${STAGEDIR}${PREFIX}/bin
-	${INSTALL_PROGRAM} ${BUILD_WRKSRC}/lib${PORTNAME}.so ${STAGEDIR}${PREFIX}/lib
+	${INSTALL_PROGRAM} ${BUILD_WRKSRC}/${PORTNAME} \
+		${STAGEDIR}${PREFIX}/bin
+	${INSTALL_LIB} ${BUILD_WRKSRC}/lib${PORTNAME}.so \
+		${STAGEDIR}${PREFIX}/lib
 
 .include <bsd.port.mk>
diff --git a/cad/abc/distinfo b/cad/abc/distinfo
index 5c2c24b2e3e8..95f59672d6af 100644
--- a/cad/abc/distinfo
+++ b/cad/abc/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1731985503
-SHA256 (berkeley-abc-abc-g20241117-1f3cf0a_GH0.tar.gz) = 2c8056d27feba4b41df6b99d392ce7c6808e35a40cb35a2dc6bdc68be5683da0
-SIZE (berkeley-abc-abc-g20241117-1f3cf0a_GH0.tar.gz) = 6265866
+TIMESTAMP = 1760019084
+SHA256 (berkeley-abc-abc-g20251002-c8eac759_GH0.tar.gz) = 2a9a93508b5474e4fe99f910fcd9663c4ea096223b5d0001769946f07737a74d
+SIZE (berkeley-abc-abc-g20251002-c8eac759_GH0.tar.gz) = 7100730
diff --git a/cad/qflow/Makefile b/cad/qflow/Makefile
index aca8ba23305b..9daae293d539 100644
--- a/cad/qflow/Makefile
+++ b/cad/qflow/Makefile
@@ -1,36 +1,37 @@
 PORTNAME=	qflow
 DISTVERSION=	1.4.104
+PORTREVISION=	1
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	End-to-end digital synthesis flow for ASIC designs
 WWW=		http://opencircuitdesign.com/qflow/
 
 LICENSE=	GPLv2
 
 APP_DEPENDS=	abc:cad/abc \
 		graywolf:cad/graywolf \
 		magic>0:cad/magic \
 		netgen-lvs>0:cad/netgen-lvs \
 		qrouter>0:cad/qrouter \
 		sta:cad/openroad \
 		yosys>0:cad/yosys
 BUILD_DEPENDS=	${APP_DEPENDS}
 RUN_DEPENDS=	${APP_DEPENDS}
 
 USES=		gmake python tar:tgz tcl tk
 USE_GITHUB=	yes
 GH_ACCOUNT=	RTimothyEdwards
 
 GNU_CONFIGURE=	yes
 
 post-patch:
 	@${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in
 	@${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in
 
 post-install:
 	@cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \
 		${STRIP_CMD} vlog2Spice vlog2Verilog vlog2Def vlog2Cel vlogFanout DEF2Verilog addspacers vesta spice2delay rc2dly blif2BSpice blif2Verilog blifFanout && \
 		${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6
 
 .include <bsd.port.mk>
diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile
index 33330596582d..86cd51a7c09e 100644
--- a/cad/yosys/Makefile
+++ b/cad/yosys/Makefile
@@ -1,64 +1,65 @@
 PORTNAME=	yosys
 DISTVERSIONPREFIX=	v
 DISTVERSION=	0.57
+PORTREVISION=	1
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Yosys Open SYnthesis Suite
 WWW=		https://yosyshq.net/yosys/ \
 		https://github.com/YosysHQ/yosys
 
 LICENSE=	ISCL
 LICENSE_FILE=	${WRKSRC}/COPYING
 
 BUILD_DEPENDS=	abc:cad/abc \
 		bash:shells/bash \
 		cxxopts>0:devel/cxxopts \
 		gawk:lang/gawk
 LIB_DEPENDS=	libffi.so:devel/libffi
 RUN_DEPENDS=	bash:shells/bash \
 		xdot:x11/py-xdot@${PY_FLAVOR}
 
 TEST_DEPENDS=	iverilog:cad/iverilog
 
 USES=		bison compiler:c++11-lang gmake pkgconfig python readline \
 		shebangfix tcl
 
 USE_GITHUB=	yes
 GH_ACCOUNT=	YosysHQ
 
 SHEBANG_FILES=	backends/smt2/smtbmc.py misc/yosys-config.in
 SHEBANG_GLOB=	*.py *.sh
 
 MAKE_ARGS=	ABCEXTERNAL=abc
 MAKE_ENV=	MAKE=${GMAKE}
 
 TEST_TARGET=	test
 
 BINARY_ALIAS=	python3=${PYTHON_CMD} tclsh=${TCLSH}
 
 OPTIONS_DEFINE=		TCMALLOC
 OPTIONS_DEFAULT=	TCMALLOC YICES # YICES: same as the default in C++ code ; TCMALLOC: should be the same default as in cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog
 OPTIONS_GROUP=		SOLVERS
 OPTIONS_GROUP_SOLVERS=	CVC5 YICES Z3
 
 CVC5_DESC=	CVC SAT Solver
 SOLVERS_DESC=	Install SAT solvers
 YICES_DESC=	Yices SAT Solver
 Z3_DESC=	Z3 SAT Solver
 
 CVC5_RUN_DEPENDS=	cvc5:math/cvc5
 TCMALLOC_LIB_DEPENDS=	libtcmalloc.so:devel/google-perftools
 TCMALLOC_LDFLAGS=	`pkg-config --libs libtcmalloc`
 YICES_RUN_DEPENDS=	yices_smt2:math/yices
 Z3_RUN_DEPENDS=		z3:math/z3
 
 post-patch:
 	${REINPLACE_CMD} -e '/^CXX =/d; s/^LD = .*/LD = $$(CXX)/' \
 		-e '/^CONFIG/s/clang/${CHOSEN_COMPILER_TYPE}/' \
 		${WRKSRC}/Makefile
 
 post-install:
 	${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
 
 .include <bsd.port.mk>