diff --git a/cad/qflow/Makefile b/cad/qflow/Makefile
index 1dd069f6eccc..57e4622dfad1 100644
--- a/cad/qflow/Makefile
+++ b/cad/qflow/Makefile
@@ -1,37 +1,36 @@
 PORTNAME=	qflow
-DISTVERSION=	1.4.100
-PORTREVISION=	1
+DISTVERSION=	1.4.102
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	End-to-end digital synthesis flow for ASIC designs
 WWW=		http://opencircuitdesign.com/qflow/
 
 LICENSE=	GPLv2
 
 APP_DEPENDS=	abc:cad/abc \
 		graywolf:cad/graywolf \
 		magic>0:cad/magic \
 		netgen-lvs>0:cad/netgen-lvs \
 		qrouter>0:cad/qrouter \
 		sta:cad/openroad \
 		yosys>0:cad/yosys
 BUILD_DEPENDS=	${APP_DEPENDS}
 RUN_DEPENDS=	${APP_DEPENDS}
 
 USES=		gmake python tar:tgz tcl tk
 USE_GITHUB=	yes
 GH_ACCOUNT=	RTimothyEdwards
 
 GNU_CONFIGURE=	yes
 
 post-patch:
 	@${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in
 	@${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in
 
 post-install:
 	@cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \
 		${STRIP_CMD} vlog2Spice vlog2Verilog vlog2Def vlog2Cel vlogFanout DEF2Verilog addspacers vesta spice2delay rc2dly blif2BSpice blif2Verilog blifFanout && \
 		${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6
 
 .include <bsd.port.mk>
diff --git a/cad/qflow/distinfo b/cad/qflow/distinfo
index a41c68b35d84..9d745284dc30 100644
--- a/cad/qflow/distinfo
+++ b/cad/qflow/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1669923941
-SHA256 (RTimothyEdwards-qflow-1.4.100_GH0.tar.gz) = 0b6c776be5b5227d0335a32ce3a1c286511fd40879f60bcc3c38f3c2135d86de
-SIZE (RTimothyEdwards-qflow-1.4.100_GH0.tar.gz) = 945741
+TIMESTAMP = 1709932742
+SHA256 (RTimothyEdwards-qflow-1.4.102_GH0.tar.gz) = 21df8fde3b36b356ee67d0f3fa4a6e013de33a4f7046de76dc01395e259a7601
+SIZE (RTimothyEdwards-qflow-1.4.102_GH0.tar.gz) = 945954