diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile
index 2abfeb8f6542..3bdaf027bdfd 100644
--- a/cad/yosys/Makefile
+++ b/cad/yosys/Makefile
@@ -1,46 +1,46 @@
 # Created by: Johnny Sorocil <jsorocil@gmail.com>
 
 PORTNAME=	yosys
 DISTVERSIONPREFIX=	yosys-
-DISTVERSION=	0.13
+DISTVERSION=	0.14
 CATEGORIES=	cad
 
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Yosys Open SYnthesis Suite
 
 LICENSE=	ISCL
 LICENSE_FILE=	${WRKSRC}/COPYING
 
 BUILD_DEPENDS=	abc:cad/abc \
 		bash:shells/bash \
 		gawk:lang/gawk
 LIB_DEPENDS=	libffi.so:devel/libffi
 RUN_DEPENDS=	xdot:x11/py-xdot@${PY_FLAVOR}
 TEST_DEPENDS=	bash:shells/bash \
 		iverilog:cad/iverilog
 
 USES=		bison compiler:c++11-lang gmake pkgconfig python:3.6+ readline \
 		shebangfix tcl
 
 SHEBANG_FILES=	backends/smt2/smtbmc.py \
 		misc/yosys-config.in
 SHEBANG_GLOB=	*.sh
 
 USE_GITHUB=	yes
 GH_ACCOUNT=	YosysHQ
 
 BINARY_ALIAS=	python3=${PYTHON_CMD} tclsh=${TCLSH}
 MAKE_ARGS=	ABCEXTERNAL=abc
 MAKE_ENV=	MAKE=${GMAKE}
 
 TEST_TARGET=	test
 
 post-patch:
 	${REINPLACE_CMD} -e '/^CXX =/d; s/^LD = .*/LD = $$(CXX)/' \
 		-e '/^CONFIG/s/clang/${CHOSEN_COMPILER_TYPE}/' \
 		${WRKSRC}/Makefile
 
 post-install:
 	${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys
 
 .include <bsd.port.mk>
diff --git a/cad/yosys/distinfo b/cad/yosys/distinfo
index 99b84f066cf4..3fc0190c37ea 100644
--- a/cad/yosys/distinfo
+++ b/cad/yosys/distinfo
@@ -1,3 +1,3 @@
-TIMESTAMP = 1642267779
-SHA256 (YosysHQ-yosys-yosys-0.13_GH0.tar.gz) = 004c203cb516887a8c76678a1fd76381198a8c46a17f4d893c34b7521df894b5
-SIZE (YosysHQ-yosys-yosys-0.13_GH0.tar.gz) = 2066136
+TIMESTAMP = 1644343025
+SHA256 (YosysHQ-yosys-yosys-0.14_GH0.tar.gz) = 8216ab178c0da7da427da806187b556c95a47322c535f2a4e0475197cdf0f2d3
+SIZE (YosysHQ-yosys-yosys-0.14_GH0.tar.gz) = 2151217
diff --git a/cad/yosys/files/patch-libs_fst_fstapi.cc b/cad/yosys/files/patch-libs_fst_fstapi.cc
new file mode 100644
index 000000000000..06efaf1a57fd
--- /dev/null
+++ b/cad/yosys/files/patch-libs_fst_fstapi.cc
@@ -0,0 +1,14 @@
+--- libs/fst/fstapi.cc.orig	2022-02-10 19:07:14 UTC
++++ libs/fst/fstapi.cc
+@@ -62,7 +62,11 @@
+ #endif
+ 
+ #ifdef HAVE_ALLOCA_H
++#if defined(__FreeBSD__)
++#include <stdlib.h>
++#else
+ #include <alloca.h>
++#endif
+ #elif defined(__GNUC__)
+ #ifndef __MINGW32__
+ #ifndef alloca
diff --git a/cad/yosys/pkg-plist b/cad/yosys/pkg-plist
index f615ad305d3b..ecef9a6c207a 100644
--- a/cad/yosys/pkg-plist
+++ b/cad/yosys/pkg-plist
@@ -1,230 +1,237 @@
 bin/yosys
 bin/yosys-config
 bin/yosys-filterlib
 bin/yosys-smtbmc
 %%DATADIR%%/abc9_map.v
 %%DATADIR%%/abc9_model.v
 %%DATADIR%%/abc9_unmap.v
 %%DATADIR%%/achronix/speedster22i/cells_map.v
 %%DATADIR%%/achronix/speedster22i/cells_sim.v
 %%DATADIR%%/adff2dff.v
 %%DATADIR%%/anlogic/arith_map.v
+%%DATADIR%%/anlogic/brams.txt
+%%DATADIR%%/anlogic/brams_init_16.vh
+%%DATADIR%%/anlogic/brams_init_8.vh
+%%DATADIR%%/anlogic/brams_init_9.vh
+%%DATADIR%%/anlogic/brams_map.v
 %%DATADIR%%/anlogic/cells_map.v
 %%DATADIR%%/anlogic/cells_sim.v
 %%DATADIR%%/anlogic/eagle_bb.v
 %%DATADIR%%/anlogic/lutram_init_16x4.vh
 %%DATADIR%%/anlogic/lutrams.txt
 %%DATADIR%%/anlogic/lutrams_map.v
 %%DATADIR%%/cells.lib
 %%DATADIR%%/cmp2lcu.v
 %%DATADIR%%/cmp2lut.v
 %%DATADIR%%/coolrunner2/cells_counter_map.v
 %%DATADIR%%/coolrunner2/cells_latch.v
 %%DATADIR%%/coolrunner2/cells_sim.v
 %%DATADIR%%/coolrunner2/tff_extract.v
 %%DATADIR%%/coolrunner2/xc2_dff.lib
 %%DATADIR%%/dff2ff.v
 %%DATADIR%%/ecp5/arith_map.v
 %%DATADIR%%/ecp5/bram_conn_1.vh
 %%DATADIR%%/ecp5/bram_conn_18.vh
 %%DATADIR%%/ecp5/bram_conn_2.vh
 %%DATADIR%%/ecp5/bram_conn_36.vh
 %%DATADIR%%/ecp5/bram_conn_4.vh
 %%DATADIR%%/ecp5/bram_conn_9.vh
 %%DATADIR%%/ecp5/bram_init_1_2_4.vh
 %%DATADIR%%/ecp5/bram_init_9_18_36.vh
 %%DATADIR%%/ecp5/brams.txt
 %%DATADIR%%/ecp5/brams_map.v
 %%DATADIR%%/ecp5/cells_bb.v
 %%DATADIR%%/ecp5/cells_ff.vh
 %%DATADIR%%/ecp5/cells_io.vh
 %%DATADIR%%/ecp5/cells_map.v
 %%DATADIR%%/ecp5/cells_sim.v
 %%DATADIR%%/ecp5/dsp_map.v
 %%DATADIR%%/ecp5/latches_map.v
 %%DATADIR%%/ecp5/lutrams.txt
 %%DATADIR%%/ecp5/lutrams_map.v
 %%DATADIR%%/efinix/arith_map.v
 %%DATADIR%%/efinix/brams.txt
 %%DATADIR%%/efinix/brams_map.v
 %%DATADIR%%/efinix/cells_map.v
 %%DATADIR%%/efinix/cells_sim.v
 %%DATADIR%%/efinix/gbuf_map.v
 %%DATADIR%%/gate2lut.v
 %%DATADIR%%/gatemate/arith_map.v
 %%DATADIR%%/gatemate/brams.txt
 %%DATADIR%%/gatemate/brams_init_20.vh
 %%DATADIR%%/gatemate/brams_init_40.vh
 %%DATADIR%%/gatemate/brams_map.v
 %%DATADIR%%/gatemate/cells_bb.v
 %%DATADIR%%/gatemate/cells_sim.v
 %%DATADIR%%/gatemate/lut_map.v
 %%DATADIR%%/gatemate/mul_map.v
 %%DATADIR%%/gatemate/mux_map.v
 %%DATADIR%%/gatemate/reg_map.v
 %%DATADIR%%/gowin/arith_map.v
 %%DATADIR%%/gowin/bram_init_16.vh
 %%DATADIR%%/gowin/brams.txt
 %%DATADIR%%/gowin/brams_init3.vh
 %%DATADIR%%/gowin/brams_map.v
 %%DATADIR%%/gowin/cells_map.v
 %%DATADIR%%/gowin/cells_sim.v
 %%DATADIR%%/gowin/lutrams.txt
 %%DATADIR%%/gowin/lutrams_map.v
 %%DATADIR%%/greenpak4/cells_blackbox.v
 %%DATADIR%%/greenpak4/cells_latch.v
 %%DATADIR%%/greenpak4/cells_map.v
 %%DATADIR%%/greenpak4/cells_sim.v
 %%DATADIR%%/greenpak4/cells_sim_ams.v
 %%DATADIR%%/greenpak4/cells_sim_digital.v
 %%DATADIR%%/greenpak4/cells_sim_wip.v
 %%DATADIR%%/greenpak4/gp_dff.lib
 %%DATADIR%%/ice40/abc9_model.v
 %%DATADIR%%/ice40/arith_map.v
 %%DATADIR%%/ice40/brams.txt
 %%DATADIR%%/ice40/brams_init1.vh
 %%DATADIR%%/ice40/brams_init2.vh
 %%DATADIR%%/ice40/brams_init3.vh
 %%DATADIR%%/ice40/brams_map.v
 %%DATADIR%%/ice40/cells_map.v
 %%DATADIR%%/ice40/cells_sim.v
 %%DATADIR%%/ice40/dsp_map.v
 %%DATADIR%%/ice40/ff_map.v
 %%DATADIR%%/ice40/latches_map.v
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl.h
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.cc
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl_capi.h
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd.h
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.cc
 %%DATADIR%%/include/backends/cxxrtl/cxxrtl_vcd_capi.h
 %%DATADIR%%/include/backends/rtlil/rtlil_backend.h
 %%DATADIR%%/include/frontends/ast/ast.h
 %%DATADIR%%/include/frontends/ast/ast_binding.h
 %%DATADIR%%/include/frontends/blif/blifparse.h
 %%DATADIR%%/include/kernel/binding.h
 %%DATADIR%%/include/kernel/celledges.h
 %%DATADIR%%/include/kernel/celltypes.h
 %%DATADIR%%/include/kernel/consteval.h
 %%DATADIR%%/include/kernel/constids.inc
 %%DATADIR%%/include/kernel/ff.h
 %%DATADIR%%/include/kernel/ffinit.h
+%%DATADIR%%/include/kernel/fstdata.h
 %%DATADIR%%/include/kernel/hashlib.h
 %%DATADIR%%/include/kernel/log.h
 %%DATADIR%%/include/kernel/macc.h
 %%DATADIR%%/include/kernel/mem.h
 %%DATADIR%%/include/kernel/modtools.h
 %%DATADIR%%/include/kernel/qcsat.h
 %%DATADIR%%/include/kernel/register.h
 %%DATADIR%%/include/kernel/rtlil.h
 %%DATADIR%%/include/kernel/satgen.h
 %%DATADIR%%/include/kernel/sigtools.h
 %%DATADIR%%/include/kernel/utils.h
 %%DATADIR%%/include/kernel/yosys.h
 %%DATADIR%%/include/libs/ezsat/ezminisat.h
 %%DATADIR%%/include/libs/ezsat/ezsat.h
+%%DATADIR%%/include/libs/fst/fstapi.h
 %%DATADIR%%/include/libs/json11/json11.hpp
 %%DATADIR%%/include/libs/sha1/sha1.h
 %%DATADIR%%/include/passes/fsm/fsmdata.h
 %%DATADIR%%/intel/common/altpll_bb.v
 %%DATADIR%%/intel/common/brams_m9k.txt
 %%DATADIR%%/intel/common/brams_map_m9k.v
 %%DATADIR%%/intel/common/ff_map.v
 %%DATADIR%%/intel/common/m9k_bb.v
 %%DATADIR%%/intel/cyclone10lp/cells_map.v
 %%DATADIR%%/intel/cyclone10lp/cells_sim.v
 %%DATADIR%%/intel/cycloneiv/cells_map.v
 %%DATADIR%%/intel/cycloneiv/cells_sim.v
 %%DATADIR%%/intel/cycloneive/cells_map.v
 %%DATADIR%%/intel/cycloneive/cells_sim.v
 %%DATADIR%%/intel/max10/cells_map.v
 %%DATADIR%%/intel/max10/cells_sim.v
 %%DATADIR%%/intel_alm/common/abc9_map.v
 %%DATADIR%%/intel_alm/common/abc9_model.v
 %%DATADIR%%/intel_alm/common/abc9_unmap.v
 %%DATADIR%%/intel_alm/common/alm_map.v
 %%DATADIR%%/intel_alm/common/alm_sim.v
 %%DATADIR%%/intel_alm/common/arith_alm_map.v
 %%DATADIR%%/intel_alm/common/bram_m10k.txt
 %%DATADIR%%/intel_alm/common/bram_m20k.txt
 %%DATADIR%%/intel_alm/common/bram_m20k_map.v
 %%DATADIR%%/intel_alm/common/dff_map.v
 %%DATADIR%%/intel_alm/common/dff_sim.v
 %%DATADIR%%/intel_alm/common/dsp_map.v
 %%DATADIR%%/intel_alm/common/dsp_sim.v
 %%DATADIR%%/intel_alm/common/lutram_mlab.txt
 %%DATADIR%%/intel_alm/common/megafunction_bb.v
 %%DATADIR%%/intel_alm/common/mem_sim.v
 %%DATADIR%%/intel_alm/common/misc_sim.v
 %%DATADIR%%/intel_alm/common/quartus_rename.v
 %%DATADIR%%/intel_alm/cyclonev/cells_sim.v
 %%DATADIR%%/machxo2/cells_map.v
 %%DATADIR%%/machxo2/cells_sim.v
 %%DATADIR%%/mul2dsp.v
 %%DATADIR%%/nexus/arith_map.v
 %%DATADIR%%/nexus/brams.txt
 %%DATADIR%%/nexus/brams_init.vh
 %%DATADIR%%/nexus/brams_map.v
 %%DATADIR%%/nexus/cells_map.v
 %%DATADIR%%/nexus/cells_sim.v
 %%DATADIR%%/nexus/cells_xtra.v
 %%DATADIR%%/nexus/dsp_map.v
 %%DATADIR%%/nexus/latches_map.v
 %%DATADIR%%/nexus/lrams.txt
 %%DATADIR%%/nexus/lrams_init.vh
 %%DATADIR%%/nexus/lrams_map.v
 %%DATADIR%%/nexus/lutrams.txt
 %%DATADIR%%/nexus/lutrams_map.v
 %%DATADIR%%/nexus/parse_init.vh
 %%DATADIR%%/pmux2mux.v
 %%DATADIR%%/python3/smtio.py
 %%DATADIR%%/quicklogic/abc9_map.v
 %%DATADIR%%/quicklogic/abc9_model.v
 %%DATADIR%%/quicklogic/abc9_unmap.v
 %%DATADIR%%/quicklogic/cells_sim.v
 %%DATADIR%%/quicklogic/lut_sim.v
 %%DATADIR%%/quicklogic/pp3_cells_map.v
 %%DATADIR%%/quicklogic/pp3_cells_sim.v
 %%DATADIR%%/quicklogic/pp3_ffs_map.v
 %%DATADIR%%/quicklogic/pp3_latches_map.v
 %%DATADIR%%/quicklogic/pp3_lut_map.v
 %%DATADIR%%/sf2/arith_map.v
 %%DATADIR%%/sf2/cells_map.v
 %%DATADIR%%/sf2/cells_sim.v
 %%DATADIR%%/simcells.v
 %%DATADIR%%/simlib.v
 %%DATADIR%%/techmap.v
 %%DATADIR%%/xilinx/abc9_model.v
 %%DATADIR%%/xilinx/arith_map.v
 %%DATADIR%%/xilinx/brams_init_16.vh
 %%DATADIR%%/xilinx/brams_init_18.vh
 %%DATADIR%%/xilinx/brams_init_32.vh
 %%DATADIR%%/xilinx/brams_init_36.vh
 %%DATADIR%%/xilinx/brams_init_8.vh
 %%DATADIR%%/xilinx/brams_init_9.vh
 %%DATADIR%%/xilinx/cells_map.v
 %%DATADIR%%/xilinx/cells_sim.v
 %%DATADIR%%/xilinx/cells_xtra.v
 %%DATADIR%%/xilinx/ff_map.v
 %%DATADIR%%/xilinx/lut4_lutrams.txt
 %%DATADIR%%/xilinx/lut6_lutrams.txt
 %%DATADIR%%/xilinx/lut_map.v
 %%DATADIR%%/xilinx/lutrams_map.v
 %%DATADIR%%/xilinx/mux_map.v
 %%DATADIR%%/xilinx/xc2v_brams.txt
 %%DATADIR%%/xilinx/xc2v_brams_map.v
 %%DATADIR%%/xilinx/xc3s_mult_map.v
 %%DATADIR%%/xilinx/xc3sa_brams.txt
 %%DATADIR%%/xilinx/xc3sda_brams.txt
 %%DATADIR%%/xilinx/xc3sda_dsp_map.v
 %%DATADIR%%/xilinx/xc4v_dsp_map.v
 %%DATADIR%%/xilinx/xc5v_dsp_map.v
 %%DATADIR%%/xilinx/xc6s_brams.txt
 %%DATADIR%%/xilinx/xc6s_brams_map.v
 %%DATADIR%%/xilinx/xc6s_dsp_map.v
 %%DATADIR%%/xilinx/xc7_brams_map.v
 %%DATADIR%%/xilinx/xc7_dsp_map.v
 %%DATADIR%%/xilinx/xc7_xcu_brams.txt
 %%DATADIR%%/xilinx/xcu_brams_map.v
 %%DATADIR%%/xilinx/xcu_dsp_map.v
 %%DATADIR%%/xilinx/xcup_urams.txt
 %%DATADIR%%/xilinx/xcup_urams_map.v