diff --git a/cad/qflow/Makefile b/cad/qflow/Makefile index 9daae293d539..862809933486 100644 --- a/cad/qflow/Makefile +++ b/cad/qflow/Makefile @@ -1,37 +1,37 @@ PORTNAME= qflow DISTVERSION= 1.4.104 -PORTREVISION= 1 +PORTREVISION= 2 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org COMMENT= End-to-end digital synthesis flow for ASIC designs WWW= http://opencircuitdesign.com/qflow/ LICENSE= GPLv2 APP_DEPENDS= abc:cad/abc \ graywolf:cad/graywolf \ magic>0:cad/magic \ netgen-lvs>0:cad/netgen-lvs \ qrouter>0:cad/qrouter \ sta:cad/openroad \ yosys>0:cad/yosys BUILD_DEPENDS= ${APP_DEPENDS} RUN_DEPENDS= ${APP_DEPENDS} USES= gmake python tar:tgz tcl tk USE_GITHUB= yes GH_ACCOUNT= RTimothyEdwards GNU_CONFIGURE= yes post-patch: @${REINPLACE_CMD} -e 's|^#!ENV_PATH python3$$|#!${PYTHON_CMD}|' ${WRKSRC}/scripts/*.py.in @${REINPLACE_CMD} -e 's|^#!TCLSH_PATH$$|#!${TCLSH}|' ${WRKSRC}/scripts/*.tcl.in post-install: @cd ${STAGEDIR}${PREFIX}/share/qflow/bin && \ ${STRIP_CMD} vlog2Spice vlog2Verilog vlog2Def vlog2Cel vlogFanout DEF2Verilog addspacers vesta spice2delay rc2dly blif2BSpice blif2Verilog blifFanout && \ ${RM} yosys-abc && ${LN} -s ${LOCALBASE}/bin/abc yosys-abc # https://github.com/RTimothyEdwards/qflow/issues/6 .include diff --git a/cad/yosys-ghdl-plugin/Makefile b/cad/yosys-ghdl-plugin/Makefile index 09e12b0faddc..ec7db547db7d 100644 --- a/cad/yosys-ghdl-plugin/Makefile +++ b/cad/yosys-ghdl-plugin/Makefile @@ -1,33 +1,33 @@ PORTNAME= yosys-ghdl-plugin PORTVERSION= g20230930 -PORTREVISION= 1 +PORTREVISION= 2 CATEGORIES= cad MAINTAINER= nsonack@herrhotzenplotz.de COMMENT= GHDL synthesis plugin for yosys WWW= https://github.com/ghdl/ghdl-yosys-plugin LICENSE= GPLv3 BUILD_DEPENDS= ghdl>0:cad/ghdl \ yosys>0:cad/yosys RUN_DEPENDS= yosys>0:cad/yosys LIB_DEPENDS= libffi.so:devel/libffi \ libghdl-5_0_1.so:cad/ghdl \ libtcmalloc.so:devel/google-perftools USES= gmake readline tcl USE_GITHUB= yes GH_ACCOUNT= ghdl GH_PROJECT= ghdl-yosys-plugin GH_TAGNAME= d44a7bccdaa458ab3ec0ce83459410604bee6c60 MAKE_ENV+= GHDL=${LOCALBASE}/bin/ghdl \ YOSYS_CONFIG=${LOCALBASE}/bin/yosys-config PLIST_FILES= share/yosys/plugins/ghdl.so post-install: ${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/ghdl.so .include diff --git a/cad/yosys-systemverilog/Makefile b/cad/yosys-systemverilog/Makefile index f7b6e2d8c631..a65978527163 100644 --- a/cad/yosys-systemverilog/Makefile +++ b/cad/yosys-systemverilog/Makefile @@ -1,97 +1,98 @@ PORTNAME= yosys-systemverilog DISTVERSION= 2023-06-14 +PORTREVISION= 1 CATEGORIES= cad PKGNAMEPREFIX= MAINTAINER= yuri@FreeBSD.org COMMENT= SystemVerilog support for Yosys WWW= https://github.com/antmicro/yosys-systemverilog LICENSE= APACHE20 LICENSE_FILE= ${WRKSRC}/LICENSE BROKEN= incompatible yet with the latest cad/uhdm, see https://github.com/antmicro/yosys-systemverilog/issues/1845 BUILD_DEPENDS= bash:shells/bash \ yosys>0:cad/yosys LIB_DEPENDS= libcapnp.so:devel/capnproto \ libffi.so:devel/libffi \ libsurelog.so:cad/surelog \ libuhdm.so:cad/uhdm RUN_DEPENDS= yosys>0:cad/yosys USES= cabal gmake pkgconfig python:build readline tcl USE_CABAL= alex-3.3.0.0 \ cmdargs-0.10.22 \ githash-0.1.6.3 \ happy-1.20.1.1 \ hashable-1.4.2.0_1 \ primitive-0.8.0.0 \ th-compat-0.1.4_2 \ vector-0.13.0.0_3 \ vector-stream-0.1.0.0_2 SKIP_CABAL_PLIST= yes # in order to update USE_CABAL run 'make local-cabal-configure local-make-use-cabal' USE_GITHUB= yes GH_ACCOUNT= antmicro GH_TAGNAME= 49069fb-${DISTVERSION} GH_TUPLE= chipsalliance:yosys-f4pga-plugins:56f957c:yosys_f4pga_plugins/yosys-f4pga-plugins \ zachjs:sv2v:6c4ee8f:sv2v/sv2v \ YosysHQ:yosys:c5e4eec:yosys/yosys MAKE_ENV= DESTDIR=${DESTDIR} \ HOME=${WRKSRC} MAKE_ARGS= YOSYS_PATH=${LOCALBASE} -j${MAKE_JOBS_NUMBER} BINARY_ALIAS= python3=${PYTHON_CMD} \ install=${FILESDIR}/install.sh OPTIONS_DEFINE= TCMALLOC OPTIONS_DEFAULT= TCMALLOC # should be the same TCMALLOC default as in cad/yosys, cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog TCMALLOC_LDFLAGS= `pkg-config --libs libtcmalloc` TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools PORTSCOUT= ignore:1 # until https://github.com/antmicro/yosys-systemverilog/issues/1798 is resolved post-extract: @${CP} ${WRKSRC_yosys}/passes/pmgen/pmgen.py ${WRKSRC}/yosys-f4pga-plugins local-cabal-configure: check-cabal @cd ${WRKSRC}/sv2v && \ ${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --dry-run --disable-benchmarks --disable-tests --flags="${CABAL_FLAGS}" ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} ${BUILD_ARGS} exe:sv2v local-make-use-cabal: check-cabal2tuple @${_CABAL2TUPLE_CMD} ${CABAL2TUPLE_ARGS} ${WRKSRC}/sv2v || (${ECHO_CMD} "Did you forget to make do-cabal-configure ?" ; exit 1) do-build: # UHDM plugin ${ECHO} "==> Building the C part (yosys-f4pga-plugins)" @cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${ALL_TARGET} # sv2v ${ECHO} "==> Building the Haskell part (sv2v)" cd ${WRKSRC}/sv2v && \ ${LN} -fs ${CABAL_DEPSDIR} && \ ${LN} -fs ../cabal.project.local && \ ${SETENV} ${MAKE_ENV} ${CABAL_HOME_ENV} ${CABAL_CMD} build --offline --disable-benchmarks --disable-tests ${CABAL_WITH_ARGS} ${CABAL_LTO_ARGS} --flags "${CABAL_FLAGS}" ${BUILD_ARGS} exe:sv2v do-install: # create directories @${MKDIR} \ ${STAGEDIR}${PREFIX}/share/yosys/plugins/fasm_extra_modules \ ${STAGEDIR}${PREFIX}/share/yosys/quicklogic/pp3 \ ${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10 \ ${STAGEDIR}${PREFIX}/share/yosys/quicklogic/qlf_k6n10f \ ${STAGEDIR}${PREFIX}/share/yosys/nexus # UHDM plugin cd ${WRKSRC}/yosys-f4pga-plugins && ${SETENV} ${MAKE_ENV} ${GMAKE} ${MAKE_ARGS} ${INSTALL_TARGET} # sv2v ${INSTALL_PROGRAM} \ ${WRKSRC}/sv2v/dist-newstyle/build/*-freebsd/ghc-*/sv2v-*/x/sv2v/build/sv2v/sv2v \ ${STAGEDIR}${PREFIX}/bin # strip binaries ${STRIP_CMD} ${STAGEDIR}${PREFIX}/share/yosys/plugins/*.so .include diff --git a/cad/yosys/Makefile b/cad/yosys/Makefile index 86cd51a7c09e..54f6353321ee 100644 --- a/cad/yosys/Makefile +++ b/cad/yosys/Makefile @@ -1,65 +1,64 @@ PORTNAME= yosys DISTVERSIONPREFIX= v -DISTVERSION= 0.57 -PORTREVISION= 1 +DISTVERSION= 0.58 CATEGORIES= cad MAINTAINER= yuri@FreeBSD.org COMMENT= Yosys Open SYnthesis Suite WWW= https://yosyshq.net/yosys/ \ https://github.com/YosysHQ/yosys LICENSE= ISCL LICENSE_FILE= ${WRKSRC}/COPYING BUILD_DEPENDS= abc:cad/abc \ bash:shells/bash \ cxxopts>0:devel/cxxopts \ gawk:lang/gawk LIB_DEPENDS= libffi.so:devel/libffi RUN_DEPENDS= bash:shells/bash \ xdot:x11/py-xdot@${PY_FLAVOR} TEST_DEPENDS= iverilog:cad/iverilog USES= bison compiler:c++11-lang gmake pkgconfig python readline \ shebangfix tcl USE_GITHUB= yes GH_ACCOUNT= YosysHQ SHEBANG_FILES= backends/smt2/smtbmc.py misc/yosys-config.in SHEBANG_GLOB= *.py *.sh MAKE_ARGS= ABCEXTERNAL=abc MAKE_ENV= MAKE=${GMAKE} TEST_TARGET= test BINARY_ALIAS= python3=${PYTHON_CMD} tclsh=${TCLSH} OPTIONS_DEFINE= TCMALLOC OPTIONS_DEFAULT= TCMALLOC YICES # YICES: same as the default in C++ code ; TCMALLOC: should be the same default as in cad/surelog, cad/uhdm because surelog's lib is used in the yosys plugin cad/yosys-systemverilog OPTIONS_GROUP= SOLVERS OPTIONS_GROUP_SOLVERS= CVC5 YICES Z3 CVC5_DESC= CVC SAT Solver SOLVERS_DESC= Install SAT solvers YICES_DESC= Yices SAT Solver Z3_DESC= Z3 SAT Solver CVC5_RUN_DEPENDS= cvc5:math/cvc5 TCMALLOC_LIB_DEPENDS= libtcmalloc.so:devel/google-perftools TCMALLOC_LDFLAGS= `pkg-config --libs libtcmalloc` YICES_RUN_DEPENDS= yices_smt2:math/yices Z3_RUN_DEPENDS= z3:math/z3 post-patch: ${REINPLACE_CMD} -e '/^CXX =/d; s/^LD = .*/LD = $$(CXX)/' \ -e '/^CONFIG/s/clang/${CHOSEN_COMPILER_TYPE}/' \ ${WRKSRC}/Makefile post-install: ${STRIP_CMD} ${STAGEDIR}${PREFIX}/bin/yosys .include diff --git a/cad/yosys/distinfo b/cad/yosys/distinfo index ae67452bc345..38209db4e411 100644 --- a/cad/yosys/distinfo +++ b/cad/yosys/distinfo @@ -1,3 +1,3 @@ -TIMESTAMP = 1758465843 -SHA256 (YosysHQ-yosys-v0.57_GH0.tar.gz) = 29ea02cb28e46f834769492176eb003c0f72245f21a3e7580aece7df06c05687 -SIZE (YosysHQ-yosys-v0.57_GH0.tar.gz) = 3399252 +TIMESTAMP = 1760017745 +SHA256 (YosysHQ-yosys-v0.58_GH0.tar.gz) = e2b8cba71da7be9009175691dade2ee98072f542e456a92d53a4f1a1bad05bd5 +SIZE (YosysHQ-yosys-v0.58_GH0.tar.gz) = 3427401 diff --git a/cad/yosys/pkg-plist b/cad/yosys/pkg-plist index 6bb02a5f2904..213697c05be5 100644 --- a/cad/yosys/pkg-plist +++ b/cad/yosys/pkg-plist @@ -1,325 +1,326 @@ bin/yosys bin/yosys-config bin/yosys-filterlib bin/yosys-smtbmc bin/yosys-witness %%DATADIR%%/abc9_map.v %%DATADIR%%/abc9_model.v %%DATADIR%%/abc9_unmap.v %%DATADIR%%/achronix/speedster22i/cells_map.v %%DATADIR%%/achronix/speedster22i/cells_sim.v %%DATADIR%%/adff2dff.v %%DATADIR%%/anlogic/arith_map.v %%DATADIR%%/anlogic/brams.txt %%DATADIR%%/anlogic/brams_map.v %%DATADIR%%/anlogic/cells_map.v %%DATADIR%%/anlogic/cells_sim.v %%DATADIR%%/anlogic/eagle_bb.v %%DATADIR%%/anlogic/lutrams.txt %%DATADIR%%/anlogic/lutrams_map.v %%DATADIR%%/cells.lib %%DATADIR%%/choices/han-carlson.v %%DATADIR%%/choices/kogge-stone.v %%DATADIR%%/choices/sklansky.v %%DATADIR%%/cmp2lcu.v %%DATADIR%%/cmp2lut.v %%DATADIR%%/cmp2softlogic.v %%DATADIR%%/coolrunner2/cells_counter_map.v %%DATADIR%%/coolrunner2/cells_latch.v %%DATADIR%%/coolrunner2/cells_sim.v %%DATADIR%%/coolrunner2/tff_extract.v %%DATADIR%%/coolrunner2/xc2_dff.lib %%DATADIR%%/dff2ff.v %%DATADIR%%/ecp5/arith_map.v %%DATADIR%%/ecp5/brams.txt %%DATADIR%%/ecp5/brams_map.v %%DATADIR%%/ecp5/cells_bb.v %%DATADIR%%/ecp5/cells_ff.vh %%DATADIR%%/ecp5/cells_io.vh %%DATADIR%%/ecp5/cells_map.v %%DATADIR%%/ecp5/cells_sim.v %%DATADIR%%/ecp5/dsp_map.v %%DATADIR%%/ecp5/latches_map.v %%DATADIR%%/ecp5/lutrams.txt %%DATADIR%%/ecp5/lutrams_map.v %%DATADIR%%/efinix/arith_map.v %%DATADIR%%/efinix/brams.txt %%DATADIR%%/efinix/brams_map.v %%DATADIR%%/efinix/cells_map.v %%DATADIR%%/efinix/cells_sim.v %%DATADIR%%/efinix/gbuf_map.v %%DATADIR%%/fabulous/arith_map.v %%DATADIR%%/fabulous/cells_map.v %%DATADIR%%/fabulous/ff_map.v %%DATADIR%%/fabulous/io_map.v %%DATADIR%%/fabulous/latches_map.v %%DATADIR%%/fabulous/prims.v %%DATADIR%%/fabulous/ram_regfile.txt %%DATADIR%%/fabulous/regfile_map.v %%DATADIR%%/gate2lut.v %%DATADIR%%/gatemate/arith_map.v %%DATADIR%%/gatemate/brams.txt %%DATADIR%%/gatemate/brams_init_20.vh %%DATADIR%%/gatemate/brams_init_40.vh %%DATADIR%%/gatemate/brams_map.v %%DATADIR%%/gatemate/cells_bb.v %%DATADIR%%/gatemate/cells_sim.v %%DATADIR%%/gatemate/inv_map.v %%DATADIR%%/gatemate/lut_map.v %%DATADIR%%/gatemate/lut_tree_cells.genlib %%DATADIR%%/gatemate/lut_tree_map.v %%DATADIR%%/gatemate/mul_map.v %%DATADIR%%/gatemate/mux_map.v %%DATADIR%%/gatemate/reg_map.v %%DATADIR%%/gowin/arith_map.v %%DATADIR%%/gowin/brams.txt %%DATADIR%%/gowin/brams_map.v %%DATADIR%%/gowin/cells_map.v %%DATADIR%%/gowin/cells_sim.v %%DATADIR%%/gowin/cells_xtra_gw1n.v %%DATADIR%%/gowin/cells_xtra_gw2a.v %%DATADIR%%/gowin/cells_xtra_gw5a.v %%DATADIR%%/gowin/lutrams.txt %%DATADIR%%/gowin/lutrams_map.v %%DATADIR%%/greenpak4/cells_blackbox.v %%DATADIR%%/greenpak4/cells_latch.v %%DATADIR%%/greenpak4/cells_map.v %%DATADIR%%/greenpak4/cells_sim.v %%DATADIR%%/greenpak4/cells_sim_ams.v %%DATADIR%%/greenpak4/cells_sim_digital.v %%DATADIR%%/greenpak4/cells_sim_wip.v %%DATADIR%%/greenpak4/gp_dff.lib %%DATADIR%%/ice40/abc9_model.v %%DATADIR%%/ice40/arith_map.v %%DATADIR%%/ice40/brams.txt %%DATADIR%%/ice40/brams_map.v %%DATADIR%%/ice40/cells_map.v %%DATADIR%%/ice40/cells_sim.v %%DATADIR%%/ice40/dsp_map.v %%DATADIR%%/ice40/ff_map.v %%DATADIR%%/ice40/latches_map.v %%DATADIR%%/ice40/spram.txt %%DATADIR%%/ice40/spram_map.v %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h %%DATADIR%%/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h %%DATADIR%%/include/backends/rtlil/rtlil_backend.h %%DATADIR%%/include/frontends/ast/ast.h %%DATADIR%%/include/frontends/ast/ast_binding.h %%DATADIR%%/include/frontends/blif/blifparse.h %%DATADIR%%/include/kernel/binding.h %%DATADIR%%/include/kernel/bitpattern.h %%DATADIR%%/include/kernel/cellaigs.h %%DATADIR%%/include/kernel/celledges.h %%DATADIR%%/include/kernel/celltypes.h %%DATADIR%%/include/kernel/consteval.h %%DATADIR%%/include/kernel/constids.inc %%DATADIR%%/include/kernel/cost.h %%DATADIR%%/include/kernel/drivertools.h %%DATADIR%%/include/kernel/ff.h %%DATADIR%%/include/kernel/ffinit.h %%DATADIR%%/include/kernel/ffmerge.h %%DATADIR%%/include/kernel/fmt.h %%DATADIR%%/include/kernel/fstdata.h %%DATADIR%%/include/kernel/gzip.h %%DATADIR%%/include/kernel/hashlib.h %%DATADIR%%/include/kernel/io.h %%DATADIR%%/include/kernel/json.h %%DATADIR%%/include/kernel/log.h %%DATADIR%%/include/kernel/macc.h %%DATADIR%%/include/kernel/mem.h %%DATADIR%%/include/kernel/modtools.h %%DATADIR%%/include/kernel/qcsat.h %%DATADIR%%/include/kernel/register.h %%DATADIR%%/include/kernel/rtlil.h %%DATADIR%%/include/kernel/satgen.h %%DATADIR%%/include/kernel/scopeinfo.h %%DATADIR%%/include/kernel/sexpr.h %%DATADIR%%/include/kernel/sigtools.h +%%DATADIR%%/include/kernel/threading.h %%DATADIR%%/include/kernel/timinginfo.h %%DATADIR%%/include/kernel/utils.h %%DATADIR%%/include/kernel/yosys.h %%DATADIR%%/include/kernel/yosys_common.h %%DATADIR%%/include/kernel/yw.h %%DATADIR%%/include/libs/ezsat/ezminisat.h %%DATADIR%%/include/libs/ezsat/ezsat.h %%DATADIR%%/include/libs/fst/fstapi.h %%DATADIR%%/include/libs/json11/json11.hpp %%DATADIR%%/include/libs/sha1/sha1.h %%DATADIR%%/include/passes/fsm/fsmdata.h %%DATADIR%%/include/passes/techmap/libparse.h %%DATADIR%%/intel/common/altpll_bb.v %%DATADIR%%/intel/common/brams_m9k.txt %%DATADIR%%/intel/common/brams_map_m9k.v %%DATADIR%%/intel/common/ff_map.v %%DATADIR%%/intel/common/m9k_bb.v %%DATADIR%%/intel/cyclone10lp/cells_map.v %%DATADIR%%/intel/cyclone10lp/cells_sim.v %%DATADIR%%/intel/cycloneiv/cells_map.v %%DATADIR%%/intel/cycloneiv/cells_sim.v %%DATADIR%%/intel/cycloneive/cells_map.v %%DATADIR%%/intel/cycloneive/cells_sim.v %%DATADIR%%/intel/max10/cells_map.v %%DATADIR%%/intel/max10/cells_sim.v %%DATADIR%%/intel_alm/common/abc9_map.v %%DATADIR%%/intel_alm/common/abc9_model.v %%DATADIR%%/intel_alm/common/abc9_unmap.v %%DATADIR%%/intel_alm/common/alm_map.v %%DATADIR%%/intel_alm/common/alm_sim.v %%DATADIR%%/intel_alm/common/arith_alm_map.v %%DATADIR%%/intel_alm/common/bram_m10k.txt %%DATADIR%%/intel_alm/common/bram_m10k_map.v %%DATADIR%%/intel_alm/common/dff_map.v %%DATADIR%%/intel_alm/common/dff_sim.v %%DATADIR%%/intel_alm/common/dsp_map.v %%DATADIR%%/intel_alm/common/dsp_sim.v %%DATADIR%%/intel_alm/common/lutram_mlab.txt %%DATADIR%%/intel_alm/common/megafunction_bb.v %%DATADIR%%/intel_alm/common/mem_sim.v %%DATADIR%%/intel_alm/common/misc_sim.v %%DATADIR%%/intel_alm/cyclonev/cells_sim.v %%DATADIR%%/lattice/arith_map_ccu2c.v %%DATADIR%%/lattice/arith_map_ccu2d.v %%DATADIR%%/lattice/brams_16kd.txt %%DATADIR%%/lattice/brams_8kc.txt %%DATADIR%%/lattice/brams_map_16kd.v %%DATADIR%%/lattice/brams_map_8kc.v %%DATADIR%%/lattice/ccu2c_sim.vh %%DATADIR%%/lattice/ccu2d_sim.vh %%DATADIR%%/lattice/cells_bb_ecp5.v %%DATADIR%%/lattice/cells_bb_xo2.v %%DATADIR%%/lattice/cells_bb_xo3.v %%DATADIR%%/lattice/cells_bb_xo3d.v %%DATADIR%%/lattice/cells_ff.vh %%DATADIR%%/lattice/cells_io.vh %%DATADIR%%/lattice/cells_map.v %%DATADIR%%/lattice/cells_sim_ecp5.v %%DATADIR%%/lattice/cells_sim_xo2.v %%DATADIR%%/lattice/cells_sim_xo3.v %%DATADIR%%/lattice/cells_sim_xo3d.v %%DATADIR%%/lattice/common_sim.vh %%DATADIR%%/lattice/dsp_map_18x18.v %%DATADIR%%/lattice/latches_map.v %%DATADIR%%/lattice/lutrams.txt %%DATADIR%%/lattice/lutrams_map.v %%DATADIR%%/microchip/LSRAM.txt %%DATADIR%%/microchip/LSRAM_map.v %%DATADIR%%/microchip/arith_map.v %%DATADIR%%/microchip/brams_defs.vh %%DATADIR%%/microchip/cells_map.v %%DATADIR%%/microchip/cells_sim.v %%DATADIR%%/microchip/polarfire_dsp_map.v %%DATADIR%%/microchip/uSRAM.txt %%DATADIR%%/microchip/uSRAM_map.v %%DATADIR%%/mul2dsp.v %%DATADIR%%/nanoxplore/arith_map.v %%DATADIR%%/nanoxplore/brams.txt %%DATADIR%%/nanoxplore/brams_init.vh %%DATADIR%%/nanoxplore/brams_map.v %%DATADIR%%/nanoxplore/cells_bb.v %%DATADIR%%/nanoxplore/cells_bb_l.v %%DATADIR%%/nanoxplore/cells_bb_m.v %%DATADIR%%/nanoxplore/cells_bb_u.v %%DATADIR%%/nanoxplore/cells_map.v %%DATADIR%%/nanoxplore/cells_sim.v %%DATADIR%%/nanoxplore/cells_sim_l.v %%DATADIR%%/nanoxplore/cells_sim_m.v %%DATADIR%%/nanoxplore/cells_sim_u.v %%DATADIR%%/nanoxplore/cells_wrap.v %%DATADIR%%/nanoxplore/cells_wrap_l.v %%DATADIR%%/nanoxplore/cells_wrap_m.v %%DATADIR%%/nanoxplore/cells_wrap_u.v %%DATADIR%%/nanoxplore/io_map.v %%DATADIR%%/nanoxplore/latches_map.v %%DATADIR%%/nanoxplore/rf_init.vh %%DATADIR%%/nanoxplore/rf_rams_l.txt %%DATADIR%%/nanoxplore/rf_rams_m.txt %%DATADIR%%/nanoxplore/rf_rams_map_l.v %%DATADIR%%/nanoxplore/rf_rams_map_m.v %%DATADIR%%/nanoxplore/rf_rams_map_u.v %%DATADIR%%/nanoxplore/rf_rams_u.txt %%DATADIR%%/nexus/arith_map.v %%DATADIR%%/nexus/brams.txt %%DATADIR%%/nexus/brams_map.v %%DATADIR%%/nexus/cells_map.v %%DATADIR%%/nexus/cells_sim.v %%DATADIR%%/nexus/cells_xtra.v %%DATADIR%%/nexus/dsp_map.v %%DATADIR%%/nexus/latches_map.v %%DATADIR%%/nexus/lrams.txt %%DATADIR%%/nexus/lrams_map.v %%DATADIR%%/nexus/lutrams.txt %%DATADIR%%/nexus/lutrams_map.v %%DATADIR%%/nexus/parse_init.vh %%DATADIR%%/pmux2mux.v %%DATADIR%%/python3/smtio.py %%DATADIR%%/python3/ywio.py %%DATADIR%%/quicklogic/common/cells_sim.v %%DATADIR%%/quicklogic/pp3/abc9_map.v %%DATADIR%%/quicklogic/pp3/abc9_model.v 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%%DATADIR%%/xilinx/xc3s_mult_map.v %%DATADIR%%/xilinx/xc3sda_dsp_map.v %%DATADIR%%/xilinx/xc4v_dsp_map.v %%DATADIR%%/xilinx/xc5v_dsp_map.v %%DATADIR%%/xilinx/xc6s_dsp_map.v %%DATADIR%%/xilinx/xc7_dsp_map.v %%DATADIR%%/xilinx/xcu_dsp_map.v