diff --git a/cad/iverilog/Makefile b/cad/iverilog/Makefile
index 741eb3fdd9c4..3b8aba2764b7 100644
--- a/cad/iverilog/Makefile
+++ b/cad/iverilog/Makefile
@@ -1,19 +1,19 @@
 # Created by: Ying-Chieh Liao <ijliao@FreeBSD.org>
 
 PORTNAME=	iverilog
 PORTVERSION=	11.0
 CATEGORIES=	cad
 MASTER_SITES=	ftp://icarus.com/pub/eda/verilog/v11/
 DISTNAME=	verilog-${PORTVERSION}
 
-MAINTAINER=	ports@FreeBSD.org
+MAINTAINER=	kbowling@FreeBSD.org
 COMMENT=	Verilog simulation and synthesis tool
 
 LICENSE=	GPLv2
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ARGS=	--disable-suffix
 
 USES=		bison compiler:c++11-lang gmake readline
 
 .include <bsd.port.mk>