diff --git a/cad/Makefile b/cad/Makefile index 17bfa30c6f12..219f0338d970 100644 --- a/cad/Makefile +++ b/cad/Makefile @@ -1,138 +1,139 @@ COMMENT = CAD tools SUBDIR += NASTRAN-95 SUBDIR += PrusaSlicer SUBDIR += abc SUBDIR += admesh SUBDIR += adms SUBDIR += alliance SUBDIR += appcsxcad SUBDIR += archimedes SUBDIR += astk-client SUBDIR += astk-serveur SUBDIR += atlc SUBDIR += basicdsp SUBDIR += brlcad SUBDIR += calculix SUBDIR += calculix-ccx SUBDIR += caneda SUBDIR += cascade SUBDIR += cascade-compiler SUBDIR += chipvault SUBDIR += csxcad SUBDIR += cura SUBDIR += cura-engine + SUBDIR += cvc SUBDIR += digital SUBDIR += dinotrace SUBDIR += ecpprog SUBDIR += electric SUBDIR += electric-ng SUBDIR += fasm SUBDIR += fdm_materials SUBDIR += feappv SUBDIR += fidocadj SUBDIR += freecad SUBDIR += freehdl SUBDIR += fritzing SUBDIR += gds3d SUBDIR += gdsreader SUBDIR += gdt SUBDIR += geda SUBDIR += gerbv SUBDIR += ghdl SUBDIR += gmsh SUBDIR += gnucap SUBDIR += gplcver SUBDIR += graywolf SUBDIR += gspiceui SUBDIR += gtkwave SUBDIR += horizon-eda SUBDIR += ifcopenshell SUBDIR += impact SUBDIR += irsim SUBDIR += iverilog SUBDIR += jspice3 SUBDIR += k40-whisperer SUBDIR += kicad SUBDIR += kicad-devel SUBDIR += kicad-doc SUBDIR += kicad-library-footprints SUBDIR += kicad-library-footprints-devel SUBDIR += kicad-library-packages3d SUBDIR += kicad-library-packages3d-devel SUBDIR += kicad-library-symbols SUBDIR += kicad-library-symbols-devel SUBDIR += kicad-library-templates SUBDIR += kicad-library-templates-devel SUBDIR += klayout SUBDIR += ktechlab SUBDIR += ldraw SUBDIR += ldview SUBDIR += leocad SUBDIR += lepton-eda SUBDIR += libopencad SUBDIR += librecad SUBDIR += libredwg SUBDIR += librepcb SUBDIR += linux-eagle5 SUBDIR += logisim SUBDIR += magic SUBDIR += meshdev SUBDIR += meshlab SUBDIR += netgen SUBDIR += netgen-lvs SUBDIR += ngspice_rework SUBDIR += nvc SUBDIR += opencascade SUBDIR += openctm SUBDIR += openfpgaloader SUBDIR += openroad SUBDIR += openscad SUBDIR += openscad-devel SUBDIR += opentimer SUBDIR += openvsp SUBDIR += oregano SUBDIR += p5-GDS2 SUBDIR += p5-Verilog-Perl SUBDIR += pcb SUBDIR += pdnmesh SUBDIR += py-cadquery SUBDIR += py-cq-editor SUBDIR += py-ezdxf SUBDIR += py-gdspy SUBDIR += py-lcapy SUBDIR += py-ocp SUBDIR += py-phidl SUBDIR += py-pyfda SUBDIR += py-pymtl SUBDIR += python-gdsii SUBDIR += qcad SUBDIR += qcsxcad SUBDIR += qelectrotech SUBDIR += qflow SUBDIR += qmls SUBDIR += qrouter SUBDIR += repsnapper SUBDIR += rubygem-gdsii SUBDIR += scotch SUBDIR += solvespace SUBDIR += sp2sp SUBDIR += spice SUBDIR += stepcode SUBDIR += stm32flash SUBDIR += sumo SUBDIR += surelog SUBDIR += sweethome3d SUBDIR += tkgate SUBDIR += tochnog SUBDIR += uhdm SUBDIR += uranium SUBDIR += verilator SUBDIR += verilog-mode.el SUBDIR += veroroute SUBDIR += xcircuit SUBDIR += yosys SUBDIR += z88 SUBDIR += zcad .include diff --git a/cad/cvc/Makefile b/cad/cvc/Makefile new file mode 100644 index 000000000000..84b75a2d1bb0 --- /dev/null +++ b/cad/cvc/Makefile @@ -0,0 +1,32 @@ +PORTNAME= cvc +DISTVERSIONPREFIX= v +DISTVERSION= 1.1.0-4 +DISTVERSIONSUFFIX= -gd172016 +CATEGORIES= cad + +MAINTAINER= yuri@FreeBSD.org +COMMENT= Circuit Validity Checker + +LICENSE= GPLv3 +LICENSE_FILE= ${WRKSRC}/LICENSE + +BUILD_DEPENDS= pyinstaller:devel/py-pyinstaller@${PY_FLAVOR} \ + bash:shells/bash + +USES= autoreconf bison gettext-runtime gettext-tools gmake python readline shebangfix +USE_GCC= yes # clang fails, see https://github.com/d-m-bailey/cvc/issues/239 + +SHEBANG_FILES= scripts/calibre_cvc scripts/clean_cvc_log scripts/expand_cells.py + +GNU_CONFIGURE= yes + +USE_GITHUB= yes +GH_ACCOUNT= d-m-bailey + +MAKE_ARGS= INTLLIBS=-lintl + +OPTIONS_DEFINE= DOCS + +PORTDOCS= * + +.include diff --git a/cad/cvc/distinfo b/cad/cvc/distinfo new file mode 100644 index 000000000000..60badc1f5ea0 --- /dev/null +++ b/cad/cvc/distinfo @@ -0,0 +1,3 @@ +TIMESTAMP = 1640757467 +SHA256 (d-m-bailey-cvc-v1.1.0-4-gd172016_GH0.tar.gz) = d09725c54079911fb4844d0df17d053b3657de6acf5a1cc187f7bd3b619a5178 +SIZE (d-m-bailey-cvc-v1.1.0-4-gd172016_GH0.tar.gz) = 328311 diff --git a/cad/cvc/files/patch-Makefile.am b/cad/cvc/files/patch-Makefile.am new file mode 100644 index 000000000000..c5fdd5a1f1b5 --- /dev/null +++ b/cad/cvc/files/patch-Makefile.am @@ -0,0 +1,10 @@ +--- Makefile.am.orig 2021-12-29 02:03:06 UTC ++++ Makefile.am +@@ -1,6 +1,6 @@ + AUTOMAKE_OPTIONS = foreign + #SUBDIRS = po src +-SUBDIRS = src scripts src_py doc ++SUBDIRS = src scripts doc + + ACLOCAL_AMFLAGS = -I m4 + diff --git a/cad/cvc/files/patch-src_Makefile.am b/cad/cvc/files/patch-src_Makefile.am new file mode 100644 index 000000000000..d07dbacaf66b --- /dev/null +++ b/cad/cvc/files/patch-src_Makefile.am @@ -0,0 +1,11 @@ +--- src/Makefile.am.orig 2021-12-29 05:59:48 UTC ++++ src/Makefile.am +@@ -1,6 +1,6 @@ + # what flags you want to pass to the C compiler & linker +-CFLAGS = -O3 +-CXXFLAGS = -O3 -std=gnu++11 ++#CFLAGS = -O3 ++CXXFLAGS += -std=gnu++11 + #LIBS = -lz -lreadline -lcurses -lhistory -lintl + LIBS = -lz -lreadline -lcurses -lhistory $(INTLLIBS) + LDFLAGS = -static-libstdc++ -static-libgcc diff --git a/cad/cvc/files/patch-src_mmap__file__pool.cpp b/cad/cvc/files/patch-src_mmap__file__pool.cpp new file mode 100644 index 000000000000..8718ccdeb8d3 --- /dev/null +++ b/cad/cvc/files/patch-src_mmap__file__pool.cpp @@ -0,0 +1,15 @@ +--- src/mmap_file_pool.cpp.orig 2021-12-28 19:09:39 UTC ++++ src/mmap_file_pool.cpp +@@ -116,7 +116,12 @@ namespace mmap_allocator_namespace { + throw mmap_allocator_exception("Error in remmap(fd)"); + + void *last_address = memory_area; ++#if defined(__FreeBSD__) ++ memory_area = mmap(last_address, size_mapped, PROT_READ, MAP_SHARED, fd, 0); ++#else + memory_area = mmap(last_address, size_mapped, PROT_READ, MAP_SHARED | MAP_NORESERVE, fd, 0); ++#endif ++ + if (memory_area == MAP_FAILED) { + if (get_verbosity() > 0) { + perror("mmap"); diff --git a/cad/cvc/files/patch-src_obstack.c b/cad/cvc/files/patch-src_obstack.c new file mode 100644 index 000000000000..313ba177999f --- /dev/null +++ b/cad/cvc/files/patch-src_obstack.c @@ -0,0 +1,11 @@ +--- src/obstack.c.orig 2021-12-28 19:08:19 UTC ++++ src/obstack.c +@@ -29,7 +29,7 @@ + # include "obstack.h" + #endif + +-#include ++//#include + + /* NOTE BEFORE MODIFYING THIS FILE: This version number must be + incremented whenever callers compiled using an old obstack.h can no diff --git a/cad/cvc/pkg-descr b/cad/cvc/pkg-descr new file mode 100644 index 000000000000..2efbc4aeb4df --- /dev/null +++ b/cad/cvc/pkg-descr @@ -0,0 +1,16 @@ +CVC: Circuit Validity Checker. Voltage aware ERC checker for CDL netlists. + +Features: +* Input netlist format is Calibre LVS CDL (Mentor, a Siemens business) +* Checks netlists with up to 4B devices (2^32). +* Power and device parameters from Microsoft Excel +* Hierarchical power files possible +* Ability to differentiate models by parameters +* Setup option to list models and power nets +* All rules are automated. No need to write rule files. +* Interactive netlist analyzer +* Script execution available +* Automatic subcircuit debug environment creation +* GUI to record error analyses results + +WWW: https://github.com/d-m-bailey/cvc diff --git a/cad/cvc/pkg-plist b/cad/cvc/pkg-plist new file mode 100644 index 000000000000..917be4f6980f --- /dev/null +++ b/cad/cvc/pkg-plist @@ -0,0 +1,11 @@ +bin/add_kisei +bin/annotate_kisei +bin/calibre_cvc +bin/clean_cvc_log +bin/cvc +bin/cvcMakefile +bin/cvc_probe.il +bin/cvc_select.tcl +bin/expand_cells.py +share/scripts/cvc/SaveCvcParameters.txt +share/scripts/cvc/box.awk