Adding the wider powerpc umbrella, so others can take a look as well.
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Wed, Jan 21
Mon, Jan 19
The type NULL checks are good. I think the whole of the changes for pmu_send() are a bit overkill. Could you test with just the one line I pointed out, and the rest reverted?
Sat, Jan 17
Fri, Jan 16
Sun, Jan 11
Impressive
Sat, Jan 3
Sun, Dec 28
Dec 20 2025
Dec 18 2025
Dec 17 2025
Avoid the extra release_host/acquire_host, since we know it's already in that taken state.
Dec 16 2025
Isn't make.conf also read for userspace builds and ports? I think we still support 32-bit userland. Would there be a corresponding change to remove the i386 bits as well?
I can't speak from authority on this, the original change almost predates my joining. @nwhitehorn made the change, and judging by the timing it was during his powerpc64 bringup, so likely related to some G5 or POWER4 issues encountered during his work. It's possible the real problem has been ironed out in the past 14 years.
Dec 12 2025
Dec 3 2025
Dec 1 2025
Nov 19 2025
Nov 6 2025
Nov 5 2025
Nov 4 2025
Committed as a935c2a63 (don't feel like reverting and updating the commit message)
Oct 30 2025
Address feedback. I hope I got everything.
Oct 29 2025
RANDOM_KEYBOARD and RANDOM_MOUSE can be masked away by sysctls. What is the need to remove them this way?
Oct 28 2025
Oct 27 2025
Oct 24 2025
I'd make the summary more like: dev/ofw: Register ofw_cpu xref.
Oct 22 2025
In D51622#1216461, @kib wrote:I really become curious in which way firmware parks APs after the initial configuration. Coreboot might have something for this.
And indeed, there is very interesting https://github.com/coreboot/coreboot/blob/main/src/cpu/x86/lapic/lapic_cpu_stop.c that is used to park APs. From my reading, they send INIT IPI to itself, which, by the claim in the source file, is equivalent to asserting the INIT# pin.
Oct 21 2025
In D51622#1179546, @kib wrote:The loop is only "Just in case" an interrupt comes in that's not disabled (not being an x86 guy, I don't know what's disabled or not with disable_intr() and lapic_disable()). If nothing can come in, then there's no need for the safe memory, since once it halts it's dead.
As I said below, I believe SMI is still possible even in 'cli;hlt' loop. On AMD there is a way to disable SMI and NMI, but I do not think the method to do that is usable for kexec, and there is also Intel without something equivalent.
Oct 20 2025
Address @kib's feedback. kexec_do_reboot() no longer takes an argument, and hasn't even in the first commit, so remove the argument from the prototype. Removed the wbinvd from the trampoline.
Oct 14 2025
Address @kib's feedback further. I didn't reproduce the problem we solved with mfence, so removed that.
Oct 7 2025
Oct 6 2025
Address @kib's feedback.
In D51623#1209399, @kib wrote:I might suggest, to not delay the commit even more, simply refuse kexec for now if we are in LA57. Then somebody would work out the missing code in the trampoline later.
In D51623#1209045, @kib wrote:It seems that you always build 4-level intermediate page table. Wouldn't it blow up if the source kernel is running in LA57 mode? [Kernel always expect LA48 on start nonetheless]
Sep 30 2025
Address feedback. I hope I got it all now.
Sep 25 2025
Sep 24 2025
Address feedback on ioctl list.
Sep 22 2025
Address feedback. I think I got it all.
Sep 17 2025
Further updates. vdso maps correctly.
Sep 10 2025
Sep 8 2025
Sep 3 2025
Aug 29 2025
Aug 25 2025
Address feedback. I think I got it all.
Aug 20 2025
Aug 14 2025
Aug 13 2025
Update after latest probe changes.
Aug 12 2025
Address @kib's feedback.
If it builds, it ships!
Address feedback. Added comment noting empty strings, and changed naked 0x12 to
the right constant.
Aug 11 2025
Aug 7 2025
In D51771#1182947, @imp wrote:Weird, all the other devices that attach via SPCR don't need this entry. Are you sure it's still needed? I reworked things a bit ago...
Or is 0x12 some super magical thing...