Index: head/cad/verilator/Makefile
===================================================================
--- head/cad/verilator/Makefile	(revision 547234)
+++ head/cad/verilator/Makefile	(revision 547235)
@@ -1,36 +1,36 @@
 # $FreeBSD$
 
 PORTNAME=	verilator
 DISTVERSION=	4.040
+PORTREVISION=	1
 CATEGORIES=	cad
 MASTER_SITES=	https://www.veripool.org/ftp/
 
-PATCH_SITES=	https://github.com/${PORTNAME}/${PORTNAME}/commit/
-PATCHFILES+=	39f16fb155b9e909f919a9d4ae06890395987b16.patch:-p1 # https://github.com/verilator/verilator/pull/2353
-
 MAINTAINER=	yuri@FreeBSD.org
 COMMENT=	Synthesizable Verilog to C++ compiler
 
 LICENSE=	GPLv3
 LICENSE_FILE=	${WRKSRC}/LICENSE
 
-USES=		bison compiler:c++14-lang gmake pathfix perl5 python:test tar:tgz
+LIB_DEPENDS=	libsystemc.so:devel/systemc
+
+USES=		bison compiler:c++14-lang gmake localbase:ldflags pathfix perl5 python:build,test tar:tgz
 
 GNU_CONFIGURE=	yes
 CONFIGURE_ENV=	INSTALL_PROGRAM="${INSTALL_SCRIPT}"
 
 TEST_TARGET=	test
 
 BINARY_ALIAS=	make=${GMAKE} python3=${PYTHON_CMD} # aliasas are only for tests
 
 post-patch:
 	${REINPLACE_CMD} -e 's|@pkgconfigdir@|${PREFIX}/libdata/pkgconfig|' \
 	    ${WRKSRC}/Makefile.in
 
 post-build:
 	@${STRIP_CMD} ${WRKSRC}/bin/verilator_bin
 
 post-install:
 	@${RM} ${STAGEDIR}${PREFIX}/bin/verilator_bin_dbg ${STAGEDIR}${PREFIX}/bin/verilator_coverage_bin_dbg
 
 .include <bsd.port.mk>
Index: head/cad/verilator/distinfo
===================================================================
--- head/cad/verilator/distinfo	(revision 547234)
+++ head/cad/verilator/distinfo	(revision 547235)
@@ -1,5 +1,3 @@
-TIMESTAMP = 1597706592
+TIMESTAMP = 1598925644
 SHA256 (verilator-4.040.tgz) = 6e1574924083922a4eb80ff22eedc866f4ce54e5fd6a34101b6af7aa29e5c0e3
 SIZE (verilator-4.040.tgz) = 2720606
-SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 266c63d54bc00d4a67163b701a10cf238faf9c21f04e0c8192bd5495ff000b80
-SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 590