D6045.1775048025.diff
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	Index: head/sys/mips/mediatek/mtk_intr_gic.c
	===================================================================
	--- head/sys/mips/mediatek/mtk_intr_gic.c
	+++ head/sys/mips/mediatek/mtk_intr_gic.c
	@@ -95,7 +95,6 @@

	static struct resource_spec mtk_gic_spec[] = {
	{ SYS_RES_MEMORY, 0, RF_ACTIVE }, /* Registers */
	- { SYS_RES_IRQ, 0, RF_ACTIVE }, /* Parent interrupt 1 */
	{ -1, 0 }
	};

	@@ -104,15 +103,8 @@
	{ NULL, 0 }
	};

	-#if 0
	-#define READ4(_sc, _reg) \
	- bus_space_read_4((_sc)->bst, (_sc)->bsh, _reg)
	-#define WRITE4(_sc, _reg, _val) \
	- bus_space_write_4((_sc)->bst, (_sc)->bsh, _reg, _val)
	-#else
	#define READ4(_sc, _reg) bus_read_4((_sc)->gic_res[0], (_reg))
	#define WRITE4(_sc, _reg, _val) bus_write_4((_sc)->gic_res[0], (_reg), (_val))
	-#endif

	static int
	mtk_gic_probe(device_t dev)
	@@ -226,12 +218,9 @@
	goto cleanup;
	}

	- if (bus_setup_intr(dev, sc->gic_res[1], INTR_TYPE_CLK,
	- mtk_gic_intr, NULL, sc, &sc->gic_intrhand)) {
	- device_printf(dev, "could not setup irq handler\n");
	- intr_pic_deregister(dev, xref);
	- goto cleanup;
	- }
	+ cpu_establish_hardintr("gic", mtk_gic_intr, NULL, sc, 0, INTR_TYPE_CLK,
	+ NULL);
	+
	return (0);

	cleanup: