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D40716.1775981746.diff
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D40716.1775981746.diff
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Index: sys/arm64/rockchip/if_dwc_rk.c
===================================================================
--- sys/arm64/rockchip/if_dwc_rk.c
+++ sys/arm64/rockchip/if_dwc_rk.c
@@ -103,6 +103,13 @@
#define SOC_CON6_GMAC_RXCLK_DLY_ENA (1 << 15)
#define SOC_CON6_RX_DL_CFG_SHIFT 8
+/* RK3308 registers */
+#define RK3308_GRF_MAC_CON0 0x04a0
+#define RK3308_MAC_SPEED_100M ((0x1 << 0) << 16 | (0x1 << 0))
+#define RK3308_MAC_SPEED_10M ((0x1 << 0) << 16 | (0x0 << 0))
+#define RK3308_INTF_SEL_RMII ((0x1 << 4) << 16 | (0x1 << 4))
+
+
struct if_dwc_rk_softc;
typedef void (*if_dwc_rk_set_delaysfn_t)(struct if_dwc_rk_softc *);
@@ -147,6 +154,9 @@
static void rk3399_set_delays(struct if_dwc_rk_softc *sc);
static int rk3399_set_speed(struct if_dwc_rk_softc *sc, int speed);
+static int rk3308_set_speed(struct if_dwc_rk_softc *sc, int speed);
+static void rk3308_set_phy_mode(struct if_dwc_rk_softc *sc);
+
static struct if_dwc_rk_ops rk3288_ops = {
};
@@ -162,10 +172,16 @@
.set_speed = rk3399_set_speed,
};
+static struct if_dwc_rk_ops rk3308_ops = {
+ .set_speed = rk3308_set_speed,
+ .set_phy_mode = rk3308_set_phy_mode,
+};
+
static struct ofw_compat_data compat_data[] = {
{"rockchip,rk3288-gmac", (uintptr_t)&rk3288_ops},
{"rockchip,rk3328-gmac", (uintptr_t)&rk3328_ops},
{"rockchip,rk3399-gmac", (uintptr_t)&rk3399_ops},
+ {"rockchip,rk3308-gmac", (uintptr_t)&rk3308_ops},
{NULL, 0}
};
@@ -338,6 +354,47 @@
return (0);
}
+static int
+rk3308_set_speed(struct if_dwc_rk_softc *sc, int speed)
+{
+ uint32_t reg;
+
+ switch (sc->base.phy_mode) {
+ case PHY_MODE_RGMII:
+ break;
+ case PHY_MODE_RMII:
+ switch (speed) {
+ case IFM_100_TX:
+ reg = RK3308_INTF_SEL_RMII | RK3308_MAC_SPEED_100M;
+ break;
+ case IFM_10_T:
+ reg = RK3308_INTF_SEL_RMII | RK3308_MAC_SPEED_10M;
+ break;
+ default:
+ device_printf(sc->base.dev, "unsupported RMII media %u\n", speed);
+ return (-1);
+ }
+
+ SYSCON_WRITE_4(sc->grf, RK3308_GRF_MAC_CON0, reg);
+ break;
+ }
+
+ return (0);
+}
+
+static void
+rk3308_set_phy_mode(struct if_dwc_rk_softc *sc)
+{
+ switch (sc->base.phy_mode) {
+ case PHY_MODE_RGMII:
+ break;
+ case PHY_MODE_RMII:
+ SYSCON_WRITE_4(sc->grf, RK3308_GRF_MAC_CON0,RK3308_INTF_SEL_RMII);
+
+ break;
+ }
+}
+
static int
if_dwc_rk_sysctl_delays(SYSCTL_HANDLER_ARGS)
{
@@ -440,7 +497,7 @@
device_printf(sc->base.dev, "could not get clk_mac_refout clock\n");
sc->clk_mac_refout = NULL;
}
-
+
clk_set_freq(sc->clk_stmmaceth, 50000000, 0);
}
}
Index: sys/arm64/rockchip/rk_grf.c
===================================================================
--- sys/arm64/rockchip/rk_grf.c
+++ sys/arm64/rockchip/rk_grf.c
@@ -55,6 +55,7 @@
{"rockchip,rk3568-pipe-grf", 1},
{"rockchip,rk3568-pipe-phy-grf", 1},
{"rockchip,rk3568-pcie3-phy-grf", 1},
+ {"rockchip,rk3308-grf", 1},
{NULL, 0}
};
Index: sys/arm64/rockchip/rk_pwm.c
===================================================================
--- sys/arm64/rockchip/rk_pwm.c
+++ sys/arm64/rockchip/rk_pwm.c
@@ -100,6 +100,7 @@
static struct ofw_compat_data compat_data[] = {
{ "rockchip,rk3288-pwm", 1 },
+ { "rockchip,rk3328-pwm", 1 },
{ "rockchip,rk3399-pwm", 1 },
{ NULL, 0 }
};
@@ -398,5 +399,8 @@
sizeof(struct rk_pwm_softc),
};
-DRIVER_MODULE(rk_pwm, simplebus, rk_pwm_driver, 0, 0);
+static devclass_t rk_pwm_devclass;
+
+EARLY_DRIVER_MODULE(rk_pwm, simplebus, rk_pwm_driver, 0, 0,
+ BUS_PASS_BUS + BUS_PASS_ORDER_LATE);
SIMPLEBUS_PNP_INFO(compat_data);
Index: sys/arm64/rockchip/rk_spi.c
===================================================================
--- sys/arm64/rockchip/rk_spi.c
+++ sys/arm64/rockchip/rk_spi.c
@@ -90,6 +90,7 @@
#define CS_MAX 1
static struct ofw_compat_data compat_data[] = {
+ { "rockchip,rk3308-spi", 1 },
{ "rockchip,rk3328-spi", 1 },
{ "rockchip,rk3399-spi", 1 },
{ "rockchip,rk3568-spi", 1 },
Index: sys/arm64/rockchip/rk_tsadc.c
===================================================================
--- sys/arm64/rockchip/rk_tsadc.c
+++ sys/arm64/rockchip/rk_tsadc.c
@@ -375,9 +375,30 @@
}
};
+static struct tsensor rk3308_tsensors[] = {
+ { .channel = 0, .id = 0, .name = "CPU"},
+ { .channel = 1, .id = 1, .name = "GPU"},
+};
+
+static struct tsadc_conf rk3308_tsadc_conf = {
+ .version = TSADC_V2,
+ .q_sel_ntc = 1,
+ .shutdown_temp = 95000,
+ .shutdown_mode = 0, /* CRU */
+ .shutdown_pol = 0, /* Low */
+ .tsensors = rk3308_tsensors,
+ .ntsensors = nitems(rk3308_tsensors),
+ .calib_info = {
+ .table = rk3328_calib_data,
+ .nentries = nitems(rk3328_calib_data),
+ }
+};
+
+
static struct ofw_compat_data compat_data[] = {
{"rockchip,rk3288-tsadc", (uintptr_t)&rk3288_tsadc_conf},
{"rockchip,rk3328-tsadc", (uintptr_t)&rk3328_tsadc_conf},
+ {"rockchip,rk3308-tsadc", (uintptr_t)&rk3328_tsadc_conf},
{"rockchip,rk3399-tsadc", (uintptr_t)&rk3399_tsadc_conf},
{"rockchip,rk3568-tsadc", (uintptr_t)&rk3568_tsadc_conf},
{NULL, 0}
Index: sys/arm64/rockchip/rk_usb2phy.c
===================================================================
--- sys/arm64/rockchip/rk_usb2phy.c
+++ sys/arm64/rockchip/rk_usb2phy.c
@@ -81,10 +81,19 @@
.disable_mask = 0x100010,
}
};
+struct rk_usb2phy_regs rk3308_regs = {
+ .clk_ctl = {
+ .offset = 0x0108,
+ .enable_mask = 0x100000,
+ /* bit 4 put pll in suspend */
+ .disable_mask = 0x100010,
+ }
+};
static struct ofw_compat_data compat_data[] = {
{ "rockchip,rk3399-usb2phy", (uintptr_t)&rk3399_regs },
{ "rockchip,rk3568-usb2phy", (uintptr_t)&rk3568_regs },
+ { "rockchip,rk3308-usb2phy", (uintptr_t)&rk3308_regs },
{ NULL, 0 }
};

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