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D40715.1776809119.diff
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D40715.1776809119.diff
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Index: sys/arm64/rockchip/rk_pinctrl.c
===================================================================
--- sys/arm64/rockchip/rk_pinctrl.c
+++ sys/arm64/rockchip/rk_pinctrl.c
@@ -1004,11 +1004,195 @@
.get_bias_value = rk3568_get_bias_value,
};
+static struct rk_pinctrl_gpio rk3308_gpio_bank[] = {
+ RK_GPIO(0, "gpio0"),
+ RK_GPIO(1, "gpio1"),
+ RK_GPIO(2, "gpio2"),
+ RK_GPIO(3, "gpio3"),
+ RK_GPIO(4, "gpio4"),
+
+};
+
+static struct rk_pinctrl_bank rk3308_iomux_bank[] = {
+ /* bank sub offs nbits */
+ RK_IOMUX(0, 0, 0x0000, 2),
+ RK_IOMUX(0, 1, 0x0004, 2),
+ RK_IOMUX(0, 2, 0x0008, 2),
+ RK_IOMUX(0, 3, 0x000C, 2),
+ RK_IOMUX(1, 0, 0x0010, 2),
+ RK_IOMUX(1, 1, 0x0014, 2),
+ RK_IOMUX(1, 2, 0x0018, 2),
+ RK_IOMUX(1, 3, 0x001C, 2),
+ RK_IOMUX(2, 0, 0x0020, 2),
+ RK_IOMUX(2, 1, 0x0024, 2),
+ RK_IOMUX(2, 2, 0x0028, 2),
+ RK_IOMUX(2, 3, 0x002C, 2),
+ RK_IOMUX(3, 0, 0x0030, 2),
+ RK_IOMUX(3, 1, 0x0034, 2),
+ RK_IOMUX(3, 2, 0x0038, 2),
+ RK_IOMUX(3, 3, 0x003C, 2),
+ RK_IOMUX(4, 0, 0x0040, 2),
+ RK_IOMUX(4, 1, 0x0044, 2),
+ RK_IOMUX(4, 2, 0x0048, 2),
+ RK_IOMUX(4, 3, 0x004C, 2),
+};
+#define RK_PINFIX_MS(bank,pin,reg,bit,mask) RK_PINFIX(bank,pin,reg,bit,(mask << bit))
+static struct rk_pinctrl_pin_fixup rk3308_pin_fixup[] = {
+ /* bank pin reg bit mask */
+ RK_PINFIX_MS(1, 14, 0x28, 12, 0xf),
+ RK_PINFIX_MS(1, 15, 0x2c, 0, 0x3),
+ RK_PINFIX_MS(1, 18, 0x30, 4, 0xf),
+ RK_PINFIX_MS(1, 19, 0x30, 8, 0xf),
+ RK_PINFIX_MS(1, 20, 0x30, 12, 0xf),
+ RK_PINFIX_MS(1, 21, 0x34, 0, 0xf),
+ RK_PINFIX_MS(1, 22, 0x34, 4, 0xf),
+ RK_PINFIX_MS(1, 23, 0x34, 8, 0xf),
+ RK_PINFIX_MS(2, 2, 0x40, 4, 0x3),
+ RK_PINFIX_MS(2, 3, 0x40, 6, 0x3),
+ RK_PINFIX_MS(2, 16, 0x50, 0, 0x3),
+ RK_PINFIX_MS(3, 10, 0x68, 4, 0x3),
+ RK_PINFIX_MS(3, 11, 0x68, 6, 0x3),
+ RK_PINFIX_MS(3, 12, 0x68, 8, 0xf),
+ RK_PINFIX_MS(3, 13, 0x68, 12, 0xf),
+};
+static struct rk_pinctrl_pin_drive rk3308_pin_drive[] = {
+ /* bank sub offs val ma */
+ RK_PINDRIVE(0, 0, 0x100, 0, 2),
+ RK_PINDRIVE(0, 0, 0x100, 1, 4),
+ RK_PINDRIVE(0, 0, 0x100, 2, 8),
+ RK_PINDRIVE(0, 0, 0x100, 3, 12),
+
+ RK_PINDRIVE(0, 1, 0x104, 0, 2),
+ RK_PINDRIVE(0, 1, 0x104, 1, 4),
+ RK_PINDRIVE(0, 1, 0x104, 2, 8),
+ RK_PINDRIVE(0, 1, 0x104, 3, 12),
+
+ RK_PINDRIVE(0, 2, 0x108, 0, 2),
+ RK_PINDRIVE(0, 2, 0x108, 1, 4),
+ RK_PINDRIVE(0, 2, 0x108, 2, 8),
+ RK_PINDRIVE(0, 2, 0x108, 3, 12),
+
+ RK_PINDRIVE(0, 3, 0x10C, 0, 2),
+ RK_PINDRIVE(0, 3, 0x10C, 1, 4),
+ RK_PINDRIVE(0, 3, 0x10C, 2, 8),
+ RK_PINDRIVE(0, 3, 0x10C, 3, 12),
+
+ RK_PINDRIVE(1, 0, 0x110, 0, 2),
+ RK_PINDRIVE(1, 0, 0x110, 1, 4),
+ RK_PINDRIVE(1, 0, 0x110, 2, 8),
+ RK_PINDRIVE(1, 0, 0x110, 3, 12),
+
+ RK_PINDRIVE(1, 1, 0x114, 0, 2),
+ RK_PINDRIVE(1, 1, 0x114, 1, 4),
+ RK_PINDRIVE(1, 1, 0x114, 2, 8),
+ RK_PINDRIVE(1, 1, 0x114, 3, 12),
+
+ RK_PINDRIVE(1, 2, 0x118, 0, 2),
+ RK_PINDRIVE(1, 2, 0x118, 1, 4),
+ RK_PINDRIVE(1, 2, 0x118, 2, 8),
+ RK_PINDRIVE(1, 2, 0x118, 3, 12),
+
+ RK_PINDRIVE(1, 3, 0x11C, 0, 2),
+ RK_PINDRIVE(1, 3, 0x11C, 1, 4),
+ RK_PINDRIVE(1, 3, 0x11C, 2, 8),
+ RK_PINDRIVE(1, 3, 0x11C, 3, 12),
+
+ RK_PINDRIVE(2, 0, 0x120, 0, 2),
+ RK_PINDRIVE(2, 0, 0x120, 1, 4),
+ RK_PINDRIVE(2, 0, 0x120, 2, 8),
+ RK_PINDRIVE(2, 0, 0x120, 3, 12),
+
+ RK_PINDRIVE(2, 1, 0x124, 0, 2),
+ RK_PINDRIVE(2, 1, 0x124, 1, 4),
+ RK_PINDRIVE(2, 1, 0x124, 2, 8),
+ RK_PINDRIVE(2, 1, 0x124, 3, 12),
+
+ RK_PINDRIVE(2, 2, 0x128, 0, 2),
+ RK_PINDRIVE(2, 2, 0x128, 1, 4),
+ RK_PINDRIVE(2, 2, 0x128, 2, 8),
+ RK_PINDRIVE(2, 2, 0x128, 3, 12),
+
+ RK_PINDRIVE(2, 3, 0x12C, 0, 2),
+ RK_PINDRIVE(2, 3, 0x12C, 1, 4),
+ RK_PINDRIVE(2, 3, 0x12C, 2, 8),
+ RK_PINDRIVE(2, 3, 0x12C, 3, 12),
+
+ RK_PINDRIVE(3, 0, 0x130, 0, 2),
+ RK_PINDRIVE(3, 0, 0x130, 1, 4),
+ RK_PINDRIVE(3, 0, 0x130, 2, 8),
+ RK_PINDRIVE(3, 0, 0x130, 3, 12),
+
+ RK_PINDRIVE(3, 1, 0x134, 0, 2),
+ RK_PINDRIVE(3, 1, 0x134, 1, 4),
+ RK_PINDRIVE(3, 1, 0x134, 2, 8),
+ RK_PINDRIVE(3, 1, 0x134, 3, 12),
+
+ RK_PINDRIVE(3, 2, 0x138, 0, 2),
+ RK_PINDRIVE(3, 2, 0x138, 1, 4),
+ RK_PINDRIVE(3, 2, 0x138, 2, 8),
+ RK_PINDRIVE(3, 2, 0x138, 3, 12),
+
+ RK_PINDRIVE(3, 3, 0x13C, 0, 2),
+ RK_PINDRIVE(3, 3, 0x13C, 1, 4),
+ RK_PINDRIVE(3, 3, 0x13C, 2, 8),
+ RK_PINDRIVE(3, 3, 0x13C, 3, 12),
+
+ RK_PINDRIVE(4, 0, 0x140, 0, 2),
+ RK_PINDRIVE(4, 0, 0x140, 1, 4),
+ RK_PINDRIVE(4, 0, 0x140, 2, 8),
+ RK_PINDRIVE(4, 0, 0x140, 4, 12),
+
+ RK_PINDRIVE(4, 1, 0x144, 0, 2),
+ RK_PINDRIVE(4, 1, 0x144, 1, 4),
+ RK_PINDRIVE(4, 1, 0x144, 2, 8),
+ RK_PINDRIVE(4, 1, 0x144, 4, 12),
+
+ RK_PINDRIVE(4, 2, 0x148, 0, 2),
+ RK_PINDRIVE(4, 2, 0x148, 1, 4),
+ RK_PINDRIVE(4, 2, 0x148, 2, 8),
+ RK_PINDRIVE(4, 2, 0x148, 4, 12),
+
+ RK_PINDRIVE(4, 4, 0x14C, 0, 2),
+ RK_PINDRIVE(4, 4, 0x14C, 1, 4),
+ RK_PINDRIVE(4, 4, 0x14C, 2, 8),
+ RK_PINDRIVE(4, 4, 0x14C, 4, 12),
+
+};
+
+static uint32_t
+rk3308_get_pd_offset(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ return (0xA0);
+}
+
+static struct syscon *
+rk3308_get_syscon(struct rk_pinctrl_softc *sc, uint32_t bank)
+{
+ return (sc->grf);
+}
+
+struct rk_pinctrl_conf rk3308_conf = {
+ .iomux_conf = rk3308_iomux_bank,
+ .iomux_nbanks = nitems(rk3308_iomux_bank),
+ .pin_fixup = rk3308_pin_fixup,
+ .npin_fixup = nitems(rk3308_pin_fixup),
+ .pin_drive = rk3308_pin_drive,
+ .npin_drive = nitems(rk3308_pin_drive),
+ .gpio_bank = rk3308_gpio_bank,
+ .ngpio_bank = nitems(rk3308_gpio_bank),
+ .get_pd_offset = rk3308_get_pd_offset,
+ .get_syscon = rk3308_get_syscon,
+ .parse_bias = rk3288_parse_bias,
+ .resolv_bias_value = rk3288_resolv_bias_value,
+ .get_bias_value = rk3288_get_bias_value,
+};
+
static struct ofw_compat_data compat_data[] = {
{"rockchip,rk3288-pinctrl", (uintptr_t)&rk3288_conf},
{"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf},
{"rockchip,rk3399-pinctrl", (uintptr_t)&rk3399_conf},
{"rockchip,rk3568-pinctrl", (uintptr_t)&rk3568_conf},
+ {"rockchip,rk3308-pinctrl", (uintptr_t)&rk3308_conf},
{NULL, 0}
};

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