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diff --git a/sys/dev/thunderbolt/nhi.c b/sys/dev/thunderbolt/nhi.c
--- a/sys/dev/thunderbolt/nhi.c
+++ b/sys/dev/thunderbolt/nhi.c
@@ -1033,6 +1033,10 @@
* descriptor, and we know if we have reached the last descriptor that the
* hardware touched. This technique saves at least 2 MEMIO reads per
* interrupt.
+ *
+ * TODO Is this actually okay? What if we fail to get a completion interrupts
+ * but hardware updated CI anyway? I know this can happen, but is this an
+ * issue?
*/
void
nhi_intr(void *data)
@@ -1053,6 +1057,16 @@
if ((r = trkr->ring) == NULL)
return;
+ /*
+ * Need to read this necessarily to clear it; see 12.6.3.4.1. Disable
+ * ISR Auto-Clear must be set to 0.
+ *
+ * XXX This might not be necessary on all platforms. It is on Pink
+ * Sardine, but this was not being done previously so it might have
+ * been working without this on whatever Scott was testing on.
+ */
+ nhi_read_reg(sc, NHI_ISR0);
+
/*
* Process TX completions from the adapter. Only go through
* the ring once to prevent unbounded looping.
diff --git a/sys/dev/thunderbolt/nhi_pci.c b/sys/dev/thunderbolt/nhi_pci.c
--- a/sys/dev/thunderbolt/nhi_pci.c
+++ b/sys/dev/thunderbolt/nhi_pci.c
@@ -383,7 +383,7 @@
tb_debug(sc, DBG_INIT, "Set up %d interrupts\n", sc->msix_count);
- /* Set the interrupt trottle rate to 128us */
+ /* Set the interrupt throttle rate to 128us */
for (i = 0; i < 16; i ++)
nhi_write_reg(sc, NHI_ITR0 + i * 4, 0x1f4);
diff --git a/sys/dev/thunderbolt/router.c b/sys/dev/thunderbolt/router.c
--- a/sys/dev/thunderbolt/router.c
+++ b/sys/dev/thunderbolt/router.c
@@ -390,6 +390,10 @@
break;
sc->inflight_cmd = NULL;
tb_debug(sc, DBG_ROUTER, "Config command timed out, retries=%d\n", retries);
+ /*
+ * TODO We might want to check if the done (DD) bit is set in
+ * the ring memory but we didn't get an interrupt.
+ */
}
if (cmd->ev != 0)
diff --git a/sys/dev/thunderbolt/tb_pcib.h b/sys/dev/thunderbolt/tb_pcib.h
--- a/sys/dev/thunderbolt/tb_pcib.h
+++ b/sys/dev/thunderbolt/tb_pcib.h
@@ -83,6 +83,8 @@
#define TB_DEV_AR_C_2C 0x15da
#define TB_DEV_ICL_0 0x8a1d
#define TB_DEV_ICL_1 0x8a21
+#define TB_DEV_PINK_SARDINE_0 0x14ef
+#define TB_DEV_PINK_SARDINE_1 0x14ea
#define TB_PCIB_VSEC(dev) ((struct tb_pcib_softc *)(device_get_softc(dev)))->vsec;
#define TB_DESC_MAX 80
diff --git a/sys/dev/thunderbolt/tb_pcib.c b/sys/dev/thunderbolt/tb_pcib.c
--- a/sys/dev/thunderbolt/tb_pcib.c
+++ b/sys/dev/thunderbolt/tb_pcib.c
@@ -105,6 +105,10 @@
"Thunderbolt 3 PCI-PCI Bridge (IceLake)" },
{ VENDOR_INTEL, TB_DEV_ICL_1, 0xffff, 0xffff, TB_GEN_TB3|TB_HWIF_ICL,
"Thunderbolt 3 PCI-PCI Bridge (IceLake)" },
+ { VENDOR_AMD, TB_DEV_PINK_SARDINE_0, 0xffff, 0xffff,
+ TB_GEN_USB4|TB_HWIF_USB4, "USB4 PCI-PCI Bridge (Pink sardine)" },
+ { VENDOR_AMD, TB_DEV_PINK_SARDINE_1, 0xffff, 0xffff,
+ TB_GEN_USB4|TB_HWIF_USB4, "USB4 PCI-PCI Bridge (Pink sardine)" },
{ 0, 0, 0, 0, 0, NULL }
};
@@ -463,7 +467,7 @@
/*
* The Upstream Facing Port (UFP) in a switch is special, it's the function
* that responds to some of the special programming mailboxes. It can't be
- * differentiated by PCI ID, so a hueristic approach to identifying it is
+ * differentiated by PCI ID, so a heuristic approach to identifying it is
* required.
*/
static int

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