D46816.1789813285.diff
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	diff --git a/sys/arm64/arm64/trap.c b/sys/arm64/arm64/trap.c
	--- a/sys/arm64/arm64/trap.c
	+++ b/sys/arm64/arm64/trap.c
	@@ -308,10 +308,18 @@
	break;
	}
	}
	- intr_enable();
	+ if (td->td_md.md_spinlock_count == 0 &&
	+ (frame->tf_spsr & PSR_DAIF_INTR) != PSR_DAIF_INTR) {
	+ MPASS((frame->tf_spsr & PSR_DAIF_INTR) == 0);
	+ intr_enable();
	+ }
	map = kernel_map;
	} else {
	- intr_enable();
	+ if (td->td_md.md_spinlock_count == 0 &&
	+ (frame->tf_spsr & PSR_DAIF_INTR) != PSR_DAIF_INTR) {
	+ MPASS((frame->tf_spsr & PSR_DAIF_INTR) == 0);
	+ intr_enable();
	+ }
	map = &td->td_proc->p_vmspace->vm_map;
	if (map == NULL)
	map = kernel_map;
	diff --git a/sys/arm64/include/armreg.h b/sys/arm64/include/armreg.h
	--- a/sys/arm64/include/armreg.h
	+++ b/sys/arm64/include/armreg.h
	@@ -2569,6 +2569,7 @@
	#define PSR_DAIF (PSR_D \| PSR_A \| PSR_I \| PSR_F)
	/* The default DAIF mask. These bits are valid in spsr_el1 and daif */
	#define PSR_DAIF_DEFAULT (0)
	+#define PSR_DAIF_INTR (PSR_I \| PSR_F)
	#define PSR_BTYPE 0x00000c00UL
	#define PSR_SSBS 0x00001000UL
	#define PSR_ALLINT 0x00002000UL